ETRI Journal
- 제28권3호
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- Pages.397-400
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- 2006
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- 1225-6463(pISSN)
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- 2233-7326(eISSN)
An Ameliorated Design Method of ML-AHB BusMatrix
- Hwang, Soo-Yun (Mobile Telecommunication Research Division, ETRI) ;
- Jhang, Kyoung-Sun (Department of Computer Engineering, Chungnam National University) ;
- Park, Hyeong-Jun (Mobile Telecommunication Research Division, ETRI) ;
- Bae, Young-Hwan (IT Convergence & Components Laboratory, ETRI) ;
- Cho, Han-Jin (IT Convergence & Components Laboratory, ETRI)
- 투고 : 2005.07.21
- 발행 : 2006.06.30
초록
The multi-layer advanced high-performance bus (ML-AHB) BusMatrix proposed by ARM is an excellent architecture for applying embedded systems with low power. However, there is one clock cycle delay for each master in the ML-AHB BusMatrix of the advanced microcontroller bus architecture (AMBA) design kit (ADK) whenever a master starts new transactions or changes the slave layers. In this letter, we propose an improved design method to remove the one clock cycle delay in the ML-AHB BusMatrix of an ADK. We also remarkably reduce the total area and power consumption of the ML-AHB BusMatrix of an ADK with the elimination of the heavy input stages.