Journal of the Institute of Electronics Engineers of Korea CI (전자공학회논문지CI)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Accelerating Symmetric and Asymmetric Cryptographic Algorithms with Register File Extension for Multi-words or Long-word Operation

다수 혹은 긴 워드 연산을 위한 레지스터 파일 확장을 통한 대칭 및 비대칭 암호화 알고리즘의 가속화

  • Lee Sang-Hoon (Department of Electronics and Computer Engineering, Korea University) ;
  • Choi Lynn (Department of Electronics Engineering, Korea University)
  • 이상훈 (고려대학교 전자컴퓨터공학과) ;
  • 최린 (고려대학교 전자공학과)
  • Published : 2006.03.01
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Abstract

In this paper, we propose a new register file architecture called the Register File Extension for Multi-words or Long-word Operation (RFEMLO) to accelerate both symmetric and asymmetric cryptographic algorithms. Based on the idea that most of cryptographic algorithms heavily use multi-words or long-word operations, RFEMLO allows multiple contiguous registers to be specified as a single operand. Thus, a single instruction can specify a SIMD-style multi-word operation or a long-word operation. RFEMLO can be applied to general purpose processors by adding instruction set for multi-words or long-word operands and functional units for additional instruction set. To evaluate the performance of RFEMLO, we use Simplescalar/ARM 3.0 (with gcc 2.95.2) and run detailed simulations on various symmetric and asymmetric cryptographic algorithms. By applying RFEMLO, we could get maximum 62% and 70% reductions in the total instruction count of symmetric and asymmetric cryptographic algorithms respectively. Also, performance results show that a speedup of 1.4 to 2.6 can be obtained in symmetric cryptographic algorithms and a speedup of 2.5 to 3.3 can be obtained for asymmetric cryptographic algorithms when we apply RFEMLO to a processor with an in-order pipeline. We also found that RFEMLO can effectively improve the performance of these cryptographic algorithms with much less cost compared to issue-width increase available in Superscalar implementations. Moreover, the RFEMLO can also be applied to Superscalar processor, leading to additional 83% and 138% performance gain in symmetric and asymmetric cryptographic algorithms.

본 연구에서는 대칭 및 비대칭 암호화 알고리즘을 가속화하기 위해, 다수 혹은 긴 워드 연산을 위한 레지스터 파일 확장 구조 (Register File Extension for Multi-words or Long-word Operation: RFEMLO)라는 새로운 레지스터 파일 구조를 제안한다. 암호화 알고리즘은 긴 워드 피연산자에 대한 명령어를 통하여 가속화 할 수 있다는 점에 착안하여, RFEMLO는 하나의 레지스터 명을 통해 여러 개의 레지스터에 접근할 수 있도록 하여 여러 연산자에 대해 동일한 연산을 수행할 수 있도록 하거나, 여러 개의 레지스터를 하나의 데이터로 사용할 수 있게 한다. RFEMLO는 긴 워드 피연산자에 대한 명령어 집합의 추가와 이를 지원하는 기능 유닛을 추가함으로서 범용 프로세서에 적용할 수 있다. 제안된 하드웨어 구조와 명령어 집합의 효율성을 평가하기 위해 Simplescalar/ARM 3.0을 사용하여 대칭 및 비대칭의 다양한 암호화 알고리즘에 적용하였다. 실험 결과, RFEMLO을 적용한 순차적 파이프라인을 가진 프로세서에서 대칭 암호화 알고리즘의 경우 $40%{\sim}160%$의 성능 향상을, 비대칭 암호화 알고리즘의 경우 $150%{\sim}230%$의 높은 성능향상을 얻을 수 있었다. RFEMLO의 적용을 통한 성능 항상은 이슈 폭의 증가를 이용한 슈퍼스칼라 구현에 따른 성능 향상과 비교할 때, 훨씬 적은 하드웨어 비용으로 효과적인 성능 향상을 얻을 수 있음을 확인하였으며 슈퍼스칼라 프로세서에 RFEMLO를 적용하는 경우에도 대칭 암호화 알고리즘에서는 최대 83.6%, 비대칭 암호화 알고리즘에서는 최대 138.6%의 추가적인 성능향상을 얻을 수 있었다.

Keywords

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