Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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A 10b 25MS/s $0.8mm^2$ 4.8mW 0.13um CMOS ADC for Digital Multimedia Broadcasting applications

DMB 응용을 위한 10b 25MS/s $0.8mm^2$ 4.8mW 0.13um CMOS A/D 변환기

  • Published : 2006.11.25
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Abstract

This work proposes a 10b 25MS/s $0.8mm^2$ 4.8mW 0.13um CMOS A/D Converter (ADC) for high-performance wireless communication systems such as DVB, DAB and DMB simultaneously requiring low voltage, low power, and small area. A two-stage pipeline architecture minimizes the overall chip area and power dissipation of the proposed ADC at the target resolution and sampling rate while switched-bias power reduction techniques reduce the power consumption of analog amplifiers. A low-power sample-and-hold amplifier maintains 10b resolution for input frequencies up to 60MHz based on a single-stage amplifier and nominal CMOS sampling switches using low threshold-voltage transistors. A signal insensitive 3-D fully symmetric layout reduces the capacitor and device mismatch of a multiplying D/A converter while low-noise reference currents and voltages are implemented on chip with optional off-chip voltage references. The employed down-sampling clock signal selects the sampling rate of 25MS/s or 10MS/s with a reduced power depending on applications. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates the measured DNL and INL within 0.42LSB and 0.91LSB and shows a maximum SNDR and SFDR of 56dB and 65dB at all sampling frequencies up to 2SMS/s, respectively. The ADC with an active die area if $0.8mm^2$ consumes 4.8mW at 25MS/s and 2.4mW at 10MS/s at a 1.2V supply.

본 논문에서는 Digital Video Broadcasting (DVB), Digital Audio Broadcasting (DAB) 및 Digital Multimedia Broadcasting (DMB) 등과 같이 저전압, 저전력 및 소면적을 동시에 요구하는 고성능 무선 통신 시스템을 위한 10b 25MS/s $0.8mm^2$ 4.8mW 0.13um CMOS A/D 변환기 (ADC)를 제안한다. 제안하는 ADC는 요구되는 해상도 및 속도 사양을 만족시키면서 동시에 면적 및 전력 소모를 최소화하기 위해 2단 파이프라인 구조를 사용하였으며, 스위치 기반의 바이어스 전력 최소화 기법(switched-bias power reduction technique)을 적용하여 전체 전력 소모를 최소화하였다. 입력단 샘플-앤-홀드 증폭기는 낮은 문턱전압을 가진 트랜지스터로 구성된 CMOS 샘플링 스위치를 사용하여 10비트 이상의 해상도를 유지하면서, Nyquist rate의 4배 이상인 60MHz의 높은 입력 신호 대역폭을 얻었으며, 전력소모를 최소화하기 위해 1단 증폭기를 사용하였다. 또한, Multiplying D/A 변환기의 커패시터 열에는 소자 부정합에 의한 영향을 최소화하기 위해서 인접신호에 덜 민감한 3차원 완전 대칭 구조의 커패시터 레이아웃 기법을 제안하며, 기준 전류 및 전압 발생기는 온-칩으로 집적하여 잡음을 최소화하면서 필요시 선택적으로 다른 크기의 기준 전압을 외부에서 인가할 수 있도록 설계하였다. 또한, 다운 샘플링 클록 신호를 사용하여 바이어스 전류를 제어함으로써 10비트의 해상도에서 응용 분야에 따라서 25MS/s 뿐만 아니라 10MS/s의 동작 속도에서 더 낮은 전력 사용이 가능하도록 하였다. 제안하는 시제품 ADC는 0.13um 1P8M CMOS 공정으로 제작되었으며 측정된 최대 DNL 및 INL은 각각 0.42LSB 및 0.91LSB 수준을 보인다. 또한, 25MS/s 및 10MS/s의 동작 속도에서 최대 SNDR 및 SFDR이 각각 56dB, 65dB이고, 전력 소모는 1.2V 전원 전압에서 각각 4.8mW, 2.4mW이며 제작된 ADC의 칩 면적은 $0.8mm^2$이다.

Keywords

References

  1. R. Wang, K. Martin, D. Johns, and G. Burra, 'A 3.3mW 12MS/s pipelined ADC in 90nm digital CMOS,' in ISSCC Dig. Tech. Papers, Feb. 2005, pp. 278-279 https://doi.org/10.1109/ISSCC.2005.1493977
  2. A. Wada, T. Kuniyuki, S. Kobayashi, and T. Sawai, 'A 14mW 10 - bit 20 - Msample/s ADC in 0.18um CMOS with 61MHz - input,' in Proc. Eur. Solid-State Circuits Conf., Sept. 2002, pp. 459-462
  3. H. C. Choi, H. J. Park, S. K. Bae, J. W. Kim, and P. Chung, 'A 1.4 V 10-bit 20 MSPS pipelined A/D converter,' in Proc. IEEE Int. Symp. Circuits and Systems, May 2000, pp. 439-442 https://doi.org/10.1109/ISCAS.2000.857125
  4. D. Y. Chang and U. K. Moon, 'A 1.4-V 10-bit 25-MS/s pipelined ADC using opamp-reset switching technique,' IEEE J. Solid-State Circuits, vol. 38, no. 8, pp. 1401-1404, May 2003 https://doi.org/10.1109/JSSC.2003.814427
  5. D. Miyazaki, M. Furuta, and S. Kawahito, 'A 16mW 30MSample/s 10b pipelined A/D converter using a pseudo-differential architecture,' in ISSCC Dig. Tech. Papers, Feb. 2002, pp. 174-458 https://doi.org/10.1109/ISSCC.2002.992992
  6. L. Jian, Z. Jianyun, S. Bo, Z. Xiaoyang, G. Yawei, and T. Ting'ao, 'A 10bit 30MSPS CMOS A/D converter for high performance video applications,' in Proc. Eur. Solid-State Circuits Conf., Sept. 2005, pp. 523-526 https://doi.org/10.1109/ESSCIR.2005.1541675
  7. H. C. Choi, J. H. Kim, S. M. Yoo, K. J. Lee, T. H. Oh, M. J. Seo, and J. W. Kim, 'A 15mW $0.2mm^{2}$ 10b 50MS/s ADC with wide input range,' in ISSCC Dig. Tech. Papers, Feb. 2006, pp. 226-227 https://doi.org/10.1109/ISSCC.2006.1696124
  8. S. T. Ryu, B. S. Song, and K. Bacrania, 'A 10b 50MS/s pipelined ADC with opamp current reuse,' in ISSCC Dig. Tech. Papers, Feb. 2006, pp. 216-217 https://doi.org/10.1109/ISSCC.2006.1696119
  9. B. Vaz, J. Goes, and N. Paulino, 'A 1.5-V 10-b 50 MS/s time-interleaved switched-opamp pipeline CMOS ADC with high energy efficiency,' in Symp. VLSI Circuits Dig. Tech. Papers, June 2004, pp. 432-435
  10. O. Stroeble, V. Dias, and C. Schwoerer, 'An 80MHz 10b pipeline ADC with dynamic range doubling and dynamic reference selection,' in ISSCC Dig. Tech. Papers, Feb. 2004, pp. 462-463 https://doi.org/10.1109/ISSCC.2004.1332794
  11. B. M. Min, P. Kim, D. Boisvert, and A. Aude, 'A 69mW 10b 80MS/s pipelined CMOS ADC,' in ISSCC Dig. Tech. Papers, Feb. 2003, pp. 324-325 https://doi.org/10.1109/ISSCC.2003.1234318
  12. Y. I. Park, S. Karthikeyan, F. Tsay, and E. Bartolome, 'A low power 10 bit, 80 MS/s CMOS pipelined ADC at 1.8V power supply,' in Proc. IEEE Int. Symp. Circuits and Systems, May 2001, pp. 580-583 https://doi.org/10.1109/ISCAS.2001.921922
  13. J. Li and U. K. Moon, 'A 1.8-V 67mW 10-bit 100MSPS pipelined ADC using time-shifted CDS technique,' in Proc. CICC, Sept. 2003, pp. 17.2.1-17.2.4 https://doi.org/10.1109/CICC.2003.1249430
  14. M. Yoshioka, M. Kudo, K. Gotoh, and Y. Watanabe, 'A 10b 125MS/s 40mW pipelined ADC in 0.18um CMOS,' in ISSCC Dig. Tech. Papers, Feb. 2005, pp. 282-283
  15. D. Kurose, T. Ito, T. Ueno, T. Yamaji, and T. Itakura, '55-mW 200-MSPS 10-bit pipeline ADCs for wireless receivers,' in Proc. Eur. Solid-State Circuits Conf., Sept. 2005, pp. 527-530 https://doi.org/10.1109/ESSCIR.2005.1541676
  16. H. W. Kim, D. K. Jeong, and W. C. Kim, 'A 30mW 8b 200MS/s pipelined CMOS ADC using a switched-opamp technique,' in ISSCC Dig. Tech. Papers, Feb. 2005, pp. 284-285 https://doi.org/10.1109/ISSCC.2005.1493980
  17. D. Y. Chang and S. H. Lee, 'Design techniques for a low-power low-cost CMOS A/D converter,' IEEE J. Solid-State Circuits, vol. 33, no. 8, pp. 1244-1248, Aug. 1998 https://doi.org/10.1109/4.705363
  18. B. L. Jeon and S. H. Lee, 'A 10b 50 MHz 320mW CMOS A/D converter for video applications,' Transactions on Consumer Electronics, vol. 45, no. 1, pp. 252-258, Feb. 1999 https://doi.org/10.1109/30.754443
  19. Y. D. Jeon and S. H. Lee, 'Acquisition time minimisation techniques for high-speed analogue signal processing,' Electron. Lett., vol. 35, pp. 1990-1991, Nov. 1999 https://doi.org/10.1049/el:19991378
  20. P. R. Gray, P. J. Hurst, S. H. Lewis, and R. G. Meyer, 'Analysis and design of analog integrated circuits,' John Wiley & Sons, 2001
  21. P. E. Allen and D. R. Holberg, 'CMOS analog circuit design,' Holt, Rinehart and Winston, 1987
  22. H. C. Choi, S. B. You, H. Y. Lee, H. J. Park, and J. W. Kim, 'A calibration-free 3V 16b 500KS/s 6mW $0.5mm^2$ ADC with 0.13um CMOS,' in Symp. VLSI Circuits Dig. Tech. Papers, June 2004, pp. 76-77
  23. S. M. Yoo, T. H. Oh, J. W. Moon, S. H. Lee, and U. K. Moon, 'A 2.5V 10b 120 MSample/s CMOS pipelined ADC with high SFDR,' in Proc. CICC, May 2002, pp. 441-444 https://doi.org/10.1109/CICC.2002.1012869
  24. Y. J. Cho and S. H. Lee, 'An 11b 70-MHz $1.2-mm^2$ 49-mW 0.18-um CMOS ADC with on-chip current/voltage references,' IEEE Transactions on Circuit and Systems I, vol. 52, no. 10, pp. 1989-1995, Oct. 2005 https://doi.org/10.1109/TCSI.2005.853251
  25. D. J. Comer and D. T. Comer, 'Using the weak inversion region to optimize input stage design of CMOS op amps,' IEEE Transactions on Circuit and Systems II, vol. 51, no. 1, pp. 8-14, Jan. 2004 https://doi.org/10.1109/TCSII.2003.821517
  26. C. Popa and D. Coada, 'A new linearization technique for a CMOS differential amplifier using bulk-driven weak inversion MOS transistors,' in Proc. IEEE Int. Symp. Circuits and Systems, vol. 2, July 2003, pp. 589-592 https://doi.org/10.1109/SCS.2003.1227121
  27. E. Seevinck, E. A. Vittoz, M. du Plessis, T. Joubert, and W. Beetge, 'CMOS translinear circuits for minimum supply voltage,' IEEE Transactions on Circuit and Systems II, vol. 47, no. 12, pp. 1560-1564, Dec. 2000 https://doi.org/10.1109/82.899656
  28. C. C. Enz and E. A. Vittoz, 'CMOS low-power analog circuit design,' Designing Low-Power Digital Systems, Emerging Technologies, pp. 79-133, May 1996 https://doi.org/10.1109/ETLPDS.1996.508872
  29. Y. J. Cho, H. H. Bae, and S. H. Lee, 'An 8b 220 MS/s 0.25 um CMOS pipeline ADC with on-chip RC-filter based voltage references,' IEICE Trans. on Electronics, vol. E88-C, no. 4, pp. 768-772, April 2005 https://doi.org/10.1093/ietele/e88-c.4.768