한국정보과학회논문지:시스템및이론 (Journal of KIISE:Computer Systems and Theory)

한국정보과학회 (Korean Institute of Information Scientists and Engineers)
권호 표지

온 칩 버스 구조와 메모리 할당에 대한 효율적인 설계 공간 탐색

Efficient Exploration of On-chip Bus Architectures and Memory Allocation

  • 김성찬 (서울대학교 전기컴퓨터공학부) ;
  • 임채석 (삼성종합기술원) ;
  • 하순회 (서울대학교 전기컴퓨터공학부)
  • 발행 : 2005.02.01
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⟨ 이전 논문 다음 논문 ⟩

초록

시스템 수준 설계에서 계산 부분과 통신 부분의 분리는 프로세서의 선택이나 기능 블록의 프로세서에 대한 할당 결과에 관계없이 설계자로 하여금 독립적인 통신 구조의 설계 공간 탐색을 가능하게 해준다. 본 논문은 버스 기반의 온 칩 통신 구조와 메모리 할당의 최적화를 위한 2단계 설계 공간 탐색 방법을 제안한다. 제안된 설계 공간 탐색 방법은 정적 성능 예측 방법을 사용하여 통신 구조에 대한 방대한 설계 공간을 빠르고 효과적으로 줄인다. 이렇게 축소된 통신 구조들의 설계 공간에 대해서는 정확한 성능 예측을 위하여 프로세서들의 메모리 트레이스론 이용한 트레이스 기반 시뮬레이션을 적용한다. 프로세서들의 동시적인 접근에 의한 버스의 충돌은 프로세서간 공유 메모리뿐 아니라 프로세서의 로컬 메모리에서도 기인하므로 메모리 할당 또한 중요하게 다루어져야 하는 부분이다. 제안된 설계 공간 탐색 방법의 효율성은 4-채널 DVR과 OFDM DVB-T용 수신기 내부의 이퀄라이저 부분을 이용하여 검증하였다.

Separation between computation and communication in system design allows the system designer to explore the communication architecture independently of component selection and mapping. In this paper we present an iterative two-step exploration methodology for bus-based on-chip communication architecture and memory allocation, assuming that memory traces from the processing elements are given from the mapping stage. The proposed method uses a static performance estimation technique to reduce the large design space drastically and quickly, and applies a trace-driven simulation technique to the reduced set of design candidates for accurate Performance estimation. Since local memory traffics as well as shared memory traffics are involved in bus contention, memory allocation is considered as an important axis of the design space in our technique. The viability and efficiency of the proposed methodology arc validated by two real -life examples, 4-channel digital video recorder (DVR) and an equalizer for OFDM DVB-T receiver.

키워드

참고문헌

  1. K. Keutzer, S. Malik, R. Newton, J. Rabaey, and A. Sangiovanni-Vincentelli, 'System-level design: Orthogonalization of concerns and platform-based design,' in IEEE Trans. Computer-Aided Design, Vol.19, pp, 1523-1543, Dec, 2000 https://doi.org/10.1109/43.898830
  2. IBM On-chip CoreConnect Bus Architecture. Available: http://www.chips.ibm.com/products/coreconnect/index.html
  3. ARM Advanced Micro Bus Architecture (AMBA). Available: http://www.arm.com/products/solutions/AMBAHomePage.html
  4. Sonics Integration Architectures, Sonics Inc. Available: http://www.sonicsinc.com
  5. K. Lahiri, A. Raghunathan, and S. Dey, 'Efficient exploration of the SoC communication architecture design space,' in Proc. Intl. Conf. Computer Aided Design, pp. 424-430, Nov, 2000 https://doi.org/10.1109/ICCAD.2000.896509
  6. T. van Meeuwen, A. Vandecappelle, A. van Zelst, and F. Catthoor, 'System-level interconnect architecture exploration for custom memory organizations,' in Proc. Intl. Symp. System Synthesis, pp. 13-18, Oct, 2001 https://doi.org/10.1145/500001.500005
  7. S. Kim, C. Im, and S. Ha, 'Schedule-aware performance estimation of communication architecture for efficient design space exploration,' in Proc. Intl. Conf. Hardware/Software Codesign and System Synthesis, pp. 195-200, Oct. 2003 https://doi.org/10.1145/944645.944697
  8. T. Yen and W. Wolf, 'Communication synthesis for distributed embedded systems,' in Proc. Intl. Conf. Computer Aided Design, pp, 288-294, Nov, 1995 https://doi.org/10.1109/ICCAD.1995.480025
  9. P. V. Knudsen and J. Madsen, 'Communication estimation for hardware/software codesign,' in Proc. Intl. Symp. Hardware/Software Codesign, pp. 55-59, Dec, 1998 https://doi.org/10.1109/HSC.1998.666238
  10. A. Nandi and R. Marculescu, 'System-level power/performance analysis for embedded systems design,' in Proc. Intl. Conf. Design Automation, pp. 599-604, Jun, 2001 https://doi.org/10.1109/DAC.2001.935579
  11. P. Lieverse, P. van der Wolf, E. Deprettere, and K. Vissers, 'A methodology for architecture exploration of heterogeneous signal processing systems,' in Proc. IEEE Workshop Signal Processing Systems, pp. 181-190, Oct, 1999 https://doi.org/10.1109/SIPS.1999.822323
  12. J. A. Rowson and A. Sangiovanni-Vincentelli, 'Interface based design,' in Proc. Intl. Conf. Design Automation, pp. 178-183, Jun, 1997 https://doi.org/10.1145/266021.266060
  13. K. Lahiri, A. Raghunathan, and S. Dey, 'System-level performance analysis for designing system-on-chip communication architecture,' in IEEE Trans. Computer-Aided Design, Vol.20, pp, 768-783, Jun, 2001 https://doi.org/10.1109/43.924830
  14. J. Gong, D. D. Gajski, and S. Bakashi, 'Model refinement for hardware-software codesign,' in Proc. European Design and Test Conference, pp. 270-274, Mar, 1996 https://doi.org/10.1109/EDTC.1996.494312
  15. M. Gasteier, M. Munch, and M. Glensner, 'Generation of interconnect topologies for communication synthesis,' in Proc. Intl. Conf, Design Automation and Test in Europe, pp. 36-43, Feb, 1998 https://doi.org/10.1109/DATE.1998.655834
  16. S. Meftali, F. Gharsalli, F. Rousseau, and A. A. Jerraya, 'An optimal memory allocation for application-specific multiprocessor system-on-chip,' in Proc. Intl. Symp. System Synthesis, pp, 19-24, Oct, 2001 https://doi.org/10.1145/500001.500006
  17. F. Frescrua, S. Pielmeier, G. Reali, G. Baruffa, and S. Cacopardi, 'DSP based OFDM demodulator and equalizer for professional DVB-T receivers,' in IEEE Trans. Broadcasting, Vol.45, pp, 323-332, Sep, 1999 https://doi.org/10.1109/11.796275