Hardware Design of Standard Hash Algorithm HAS-160

  • Youn Choong-Mo (School of Information Technology, Seoil College) ;
  • Lee Beom-Geun (Department of Electronic Engineering, Kyunghee University)
  • 발행 : 2005.12.01

초록

This paper is about the hardware implementation of the Hash algorithm, HAS-160, which is widely used for Internet security and authentication. VHDL modeling was used for its realization and the operation speed has been increased by the optimized scheduling of the operations required for step operations.

키워드

참고문헌

  1. TTAS.KO-12.0011/R1 (2000): Hash function Algorithm Standard (HAS-160)
  2. Douglas R. Stinson, Cryptography Theory and Practice, CRC, 1995
  3. J. Touch, 'Report on MD5 performance' RFC 1810, June 1995
  4. Janaka Deepakumara, Howard M. Heys and R. Venkatesan, 'FPGA IMPLEMENTATION OF MD5 HASH ALGORITHM' Technical Paper, Engineering and Applied Science Memorial University of Newfoundland St. John Canada, 2001
  5. Warwick Ford, Computer Communications Security, Prentice-Hall International Inc, 1994
  6. Man Young Rhee, Cryptography and Secure Communications, McGraw-Hill, 1994
  7. Bruce Schneier, Applied Cryptography, John Wiley & Sons Inc. 1996