결정도에 기초한 다중출력조합디지털논리시스템

Multiple-Output Combinational Digital Logic Systems based on Decision Diagram

  • 박춘명 (충주대학교 전기 전자 및 정보공학부 컴퓨터공학과)
  • 발행 : 2005.10.01

초록

본 논문에서는 TDBM과 CMTEDD를 사용하여 다중출력조합디지털논리시스템 설계방법의 한가지를 제안하였다. 또한, CBDD와 CMTEDD를 기반으로 최종 조합디지털논리시스템 구성을 멀티플렉서를 사용하여 구현하였다. 제안한 방법은 기존의 방법에 비해 모듈사이의 내부결선을 효과적으로 줄일 수 있으며 입력변수의 쌍과 출력함수의 쌍에 의해 게이트 수를 줄일 수 있는 장점이 있다.

This paper presents a design method for multiple-output combinational digital logic systems using time domain based on multiplexing(TDBM) and common multi-terminal extension decision diagrams(CMTEDD). The CMIEDDs represents extension valued multiple-output functions, while TDBM systems transmit several signals on a single lines. The proposed method can reduce the 1)hardware, 2)logic levels and 3)pins. In the logic system design, we use two types of decision diagrams(DDs), that is the common binary decision diagrams(CBDDs) and CMTEDDs. Also, we propose an algorithms to derive common multiple-terminal binary decision diagrams(CMTBDD) from CBDDs, and CMTEDDs from CMTBDDs. The CMTEDDs over CBDDs is more compactness in terms of number of non-terminal nodes, where the nodes for output selection variables are not included in the non-terminal nodes. In the logic design, each non-terminal nodes of an CBDDs and an CMTEDDs is realized by a multiplexer(MUX). In addition, we compare the proposed TDBM realization with the conventional one.

키워드

참고문헌

  1. D. B. West, Introduction to Graph Theory, Prentice-hall, 1996
  2. R.J.Wilson and J.J.Watkihs, GRAPHS An Introductory Approach, John Wiley & Sons, Inc., 1990
  3. S.B.Aker, 'Binary Decision Diagrams,' IEEE Trans. Comput., vol.C-27, no.6, pp.059-516, Jun. 1978
  4. R.E.Bryant, 'Graph-Based Algorithms for Boolean Function manipulations,' IEEE Trans. Comput., vol.C-35, no.8, pp.677-691, Aug. 1986 https://doi.org/10.1109/TC.1986.1676819
  5. Yung- Te Lai, M.Pedram and S.B.K. Vrudhula, 'Formal Verification Using Edge-Valued Binary Decision Diagrams,' IEEE Trans. on Computers, Vol. 45, No.2, February 1996
  6. M.Nakajima and M.Kameyama, 'Design of Highly Parallel Linear Digital System for ULSI Processors', IEICE Trans, VoI.E76-C, No.7, pp.1119-1125, July, 1993
  7. H.Jiang, J.C.Majithia, 'Suggestion for a New Representation for Bianary Function,' IEEE Trans. Comput. vol.45, no.12, pp.1445-1449, Dec. 1996 https://doi.org/10.1109/12.545975
  8. R.K.Brayton, G.D.Hachtel, C.T.McMullen and A.L.Sangionanni-Vincentelli, Logic Minimization Algorithms for VLSI Synthesis, Kluwer Academic Publishers, 1984