Preparation of Field Effect Transistor with $(Bi,La)Ti_3O_{12}$ Gate Film on $Y_2O_3/Si$ Substrate

  • Chang Ho Jung (Department of Electronics Engineering, Dankook University) ;
  • Suh Kwang Jong (Department of Electrical and Electronics Engineering, Toyohashi University of Technology) ;
  • Suh Kang Mo (Department of Electronics Engineering, Dankook University) ;
  • Park Ji Ho (Department of Electronics Engineering, Dankook University) ;
  • Kim Yong Tae (Semi-conductor Materials and Devices Lab., Korea Institute of Science and Technology) ;
  • Chang Young Chul (School of Mechatronics Engineering, Korea University of Technology and Education)
  • 발행 : 2005.03.01

초록

The field effect transistors (FETs) were fabricated ell $Y_2O_3/Si(100)$ substrates by the conventional memory processes and sol-gel process using $(Bi,La)Ti_3O_{12}(BLT)$ ferroelectric gate materials. The remnant polarization ($2Pr = Pr^+-Pr^-$) int Pt/BLT/Pt/Si capacitors increased from $22 {\mu}C/cm^2$ to $30{\mu}C/ cm^2$ at 5V as the annealing temperature increased from $700^{\circ}C$ to $750^{\circ}C$. There was no drastic degradation in the polarization values after applying the retention read pulse for $10^{5.5}$ seconds. The capacitance-voltage data of $Pt/BLT/Y_2O_3/Si$ capacitors at 5V input voltage showed that the memory window voltage decreased from 1.4V to 0.6V as the annealing temperature increased from $700^{\circ}C$ to $750^{\circ}C$. The leakage current of the $Pt/BLT/Y_2O_3/Si$ capacitors annealed at $750^{\circ}C$ was about $510^{-8}A/cm^2$ at 5V. From the drain currents versus gate voltages ($V_G$) for $Pt/BLT/Y_2O_3/Si(100)$ FET devices, the memory window voltages increased from 0.3V to 0.8V with increasing tile $V_G$ from 3V to 5V.

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