Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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A switch-matrix semidigital FIR reconstruction filter for a high-resolution delta-sigma D/A converter

스위치-매트릭스 구조의 고해상도 델타-시그마 D/A변환기용 준 디지털 FIR 재생필터

  • Song, Yun-Seob (Department of Electronics and Computer Engineering, Korea University) ;
  • Kim, Soo-Won (Department of Electronics and Computer Engineering, Korea University)
  • 송윤섭 (고려대학교 전자컴퓨터공학과) ;
  • 김수원 (고려대학교 전자컴퓨터공학과)
  • Published : 2005.07.01
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Abstract

An area efficient, low power switch-matrix semidigital FIR reconstruction filter for delta-sigma D/A converter is proposed. Filter coefficients are quantified to 7-bit and 7 current sources that correspond to each coefficient bit are used. The proposed semidigital FIR reconstruction filter is designed in a 0.25 um CMOS process and incorporates 1.5 mm$^{2}$ of active area and a power consumption is 3.8 mW at 2.5 V supply. The number of switching transistors is 1419 at 205 filter order. Simulation results show that the filter output has a dynamic range of 104 dB and 84 dB attenuation of out-of-band quantization noise.

본 논문에서는 작은 면적을 갖는 저전력 스위치-매트릭스 구조의 델타-시그마 D/A 변환기용 준 디지털 FIR 재생필터를 제안하였다. 제안된 재생필터는 계수를 7 비트로 양자화하고 각 비트 값에 대응하는 전류를 생성하는 7 개의 전류원을 사용하는 구조로 205 개의 탭을 가지며 1419 개의 스위칭 트랜지스터로 구현되었다. 제안된 필터는 0.25 um CMOS공정을 이용하여 설계되었으며 전체 칩 면적은 1.5 mm$^{2}$으로 2.5 V에서 3.8 mW의 소비 전력을 갖는다. 모의실험 결과 104 dB의 다이나믹 레인지와 -84 dB의 대역 밖의 노이즈 허용값을 나타내어 고해상도 오디오용 DAC에 적합하다.

Keywords

References

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