The KIPS Transactions:PartA (정보처리학회논문지A)

Korea Information Processing Society (한국정보처리학회)
권호 표지
DOI QR코드

DOI QR Code

On the Conceptual Design of the SIMD Vector Machine Attachable to SISD Machine

SISD 머신에 부착 가능한 SIMD 벡터 머신의 개념적 설계

  • 조영일 (한림대학교 정보통신공학부) ;
  • 고영웅 (한림대학교 정보통신공학부)
  • Published : 2005.06.01
Download PDF
⟨ Previous Next ⟩

Abstract

The addressing mode for data is performed by the software in yon Neumann-concept(SISD) computer a priori without hardware design of an address counter for operands. Therefore, in the addressing mode for the vector the corresponding variables as much as the number of the elements should be specified and used also in the software method. This is because not for operand but only for an instructions, quasi PC(program counter) is designed in hardware physically. A vector has a characteristic of a structural dimension. In this paper we propose to design a hardware unit physically external to the CPU for addressing only the elements of a vector unit with the structure and dimension. Because of the high speed performance for a vector processing it should be designed in the SIMD pipeline mechanics. The proposed mechanics is evaluated through a simulation. Our result shows $12\%$ to $30\%$ performance enhancement over CRAY architecture under the same hardware consideration(processing unit).

데이터 주소의 계수를 위한 하드웨어 설계가 없는 본 노이만(von Neuman) 개념(SISD)의 컴퓨터에서 데이터의 주소지정은 소프트웨어적으로 수행된다. 그러므로 벡터 데이터 요소들의 주소지정은 인덱싱 기법에 의해 그 요소 수만큼 해당 변수들을 만들어서 사용해야 한다. 이것은 데이터 계수기 없이 명령어 계수기, 즉 PC(program counter)만 하드웨어로 설계되기 때문이다. 본 연구에서는 중앙처리장치 외부에 외형적 구조와 크기를 갖는 단위 벡터의 요소를 액세스하는 하드웨어 유닛의 설계를 제안한다. 벡터 처리는 고속처리가 전제되기 때문에 파이프라인 처리기법(SIMD)으로 설계되어야 한다. 제안한 방법은 시뮬레이션을 통하여 성능 검증을 하였으며, 실험 결과 동일한 프로세싱 유닛을 가지는 벡터 머신 아키텍쳐보다 $12-30\%$ 정도 우수한 성능을 내는 것을 확인하였다.

Keywords

References

  1. R.M. Russell, 'The CRAY-I Computer System,' Cray Research Inc. 1986
  2. F. Boeri and M. Auguin, 'OPSlLA : A Vector and Parallel Processor,' IEEE Trans. on Comput., Vol. 42, No.1, Jan., 1993. pp.76-82 https://doi.org/10.1109/12.192215
  3. K.L.Chung, W.M.Yan, 'Fast Vectorization for Calculating a Moving Sum,' IEEE Trans. on Comput., Vol.44, Nov., 1995 https://doi.org/10.1109/12.475130
  4. J.Backus, 'Can Programming Be Liberated from the von Neumann Style? A Functional Style and Its Algebra of Programs,' CVCM 21, 8, 1978. pp.613-641 https://doi.org/10.1145/359576.359579
  5. Yuan Lin, Nadav Baron, Hyunseok Lee, Scott Mahlke, and Trevor Mudge,'A Programmable Vector Coprocessor Architecture for Wireless Applications', Proc. 3rd Workshop on Application Specific Processors, Sep., 2004
  6. C. Kozyrakis, J. Gebis, D. Martin, et aI., 'VIRAM: A Media-oriented V ector Processor with Embedded DRAM,' In the Conference Record of the Hot Chips XII Symposium, Palo Alto, CA, August, 2000
  7. C. Kozyrakis. 'A Media-enhanced Vector Architecture for Embedded Memory Systems,' Technical Report CSD99-1059, Computer Science Division, University of California at Berkeley, 1999
  8. C. Kozyrakis. Scalable Vector Media-processors for Embedded Systems. PhD thesis, University of California at Berkeley, 2002
  9. C. Kozyrakis and D. Patterson. 'Vector vs. superscalar and vliw architectures for embedded multimedia benchmarks,' In MICRO, Nov., 2002 https://doi.org/10.1109/MICRO.2002.1176257
  10. G. Sohi. 'High-bandwidth Interleaved Memories for Vector Processors - A Simulation Study,' IEEE Transactions on Computers, 42(1):34{45, January, 1993 https://doi.org/10.1109/12.192212
  11. J.E. Smith and W.R. Taylor. 'Characterizing Memory Performance in Vector Multi-processors,' In the Proceedings of the IntI. Conference on Supercomputing, pages 35-44, Minneapolis, MN, July, 1992
  12. J. H. Ahn et al. 'Evaluating the imagine stream architecture,' In ISCA, Jun. 2004. Publishing, 1997 https://doi.org/10.1109/ISCA.2004.1310760
  13. M. Bedford et al. 'Evaluation of the raw microprocessor: An exposed-wire-delay architecture for ilp and streams,' In ISCA, Jun., 2004 https://doi.org/10.1109/ISCA.2004.1310759
  14. K. Asanovic. Vector Microprocessors. PhD thesis, Computer Science Division, University of California at Berkeley, 1998
  15. R. Espasa and M. Valero. 'Decoupled V ector Architecture,' In the Proceedings of the 2nd IntI. Symposium on High-Performance Computer Architecture, San Jose, CA, February, 1996
  16. J.D. Gee and A.J. Smith. 'The Performance Impact of Vector Processor Caches,' In the Proceedings of the 25th Hawaii IntI. Conference on System Sciences, pp.437-449, January, 1992 https://doi.org/10.1109/HICSS.1992.183193
  17. D.H.Bailey, 'Vector Computer Memory Bank Contention,' IEEE Trans. on Comput., vol. c-36, No.3, Mar., 1987. pp.293-297 https://doi.org/10.1109/TC.1987.1676901
  18. A.L.Decegama, The Technology of Parallel Processing, Parallel Processing Architectures and VLSI Hardware vol. 1, Prentice-Hall Int.Editions 1989. pp.71-77, 166-177
  19. Y.i.CHO, 'A Design of the Dedicated Functional Unit for Reductive Operation in Pipeline Processing,' Proceedings of PARALLEL PROCESSING SYSTEM, Vol. 9, No.3, September, 1998
  20. Y.i.CHO, H.R.Kweon, 'On Design for Elimination of the Merging Delay Time in the Multiple Vector Reduction(Inner Product),' THE TRANS. OF THE KOREA INFORMATION PROCESSING SOCIETY, Vol. 7, No. 12, Dec., 2000
  21. F. Ayres, Jr, 'Theory and Problems of Matrices,' Si(metric) edition, SCHAUM'S OUTLINE SERIES, 1974. McGraw-Hill