References
- Y. Zorian, E.J. Marinissen, and S. Dey, 'Testing embedded core-based system chips,' IEEE Computer, Volume 32, Number, 6, pp.52-60, June 1999 https://doi.org/10.1109/2.769444
- Erik Jan Marinissen, Yervant Zorian, Rohit Kapur, Tony Taylor, Lee Whetsel, 'Towards a Standard for Embedded Core Test: An Example,' Proc. International Test Conference, pp.616-627, 1999 https://doi.org/10.1109/TEST.1999.805786
- P1500 Scalable Architecture Task Force Members, 'Preliminary Outline of the IEEE P1500 Scalable Architecture for Testing Embedded Cores,' Proc. VLSI Test Symposium, 1999
- Immaneni, V., and S.Raman, 'Direct Access Test Scheme - Design of Block and Core Cells for Embedded ASICS,' Proc. International Test Conference, pp.488-492, 1990 https://doi.org/10.1109/TEST.1990.114058
- Peter Harrod, 'Testing Reusable IF - A Case Study,' Proc. International Test Conference, pp.493-498, 1999 https://doi.org/10.1109/TEST.1999.805772
- Lee Whetsel, 'Addressable Test Ports An Approach to Testing Embedded Cores,' Proc. International Test Conference, PP.1055-1064, 1999 https://doi.org/10.1109/TEST.1999.805839
- IEEE P1500 General Working Group website, 'IEEE P1500 Standards For Embedded Core Test,' http://grouper.ieee.org/groups/1500/
- Yervant Zorian, Erik Jan Marinissen, and Sujit Dey, 'Testing Embedded-Core Based System Chips,' Proc. International Test Conference, pp.130-243, 1998 https://doi.org/10.1109/TEST.1998.743146
- Marinissen, E.J., Gael, S.K., Lousberg, M., 'Wrapper Design for Embedded Core. Test,' Proc. International Test Conference, pp.911-920, 2000 https://doi.org/10.1109/TEST.2000.894302
- Iyengar. V., Chakrabarty. K., Marinissen, E.J., 'Test wrapper and test access mechanism co-optimization for system-on-chip,' Proc. International Test Conference, pp.1023-1032, 2001 https://doi.org/10.1109/TEST.2001.966728
- Prab Varma, Sandeep Bhatia, 'A Structured Test Re-Use Methodology for Systems on Silicon,' Proc. International Test Conference, pp.294-302, 1998 https://doi.org/10.1109/TEST.1998.743167
- E. J. Marinissen, R, Arendsen, G. Bos, H. Dingemanse, M. Lousberg, and C. Wouters, 'A Structured and Scalable Mechanism for Test Access to Embedded Reusable Cores,' Proc. International Test Conference, pp.284-293, 1998 https://doi.org/10.1109/TEST.1998.743166
- IEEE Computer Society, IEEE Standard Test Access Port and Boundary-Scan Architecture-IEEE Std 1149.1-1990, IEEE, New York, 1990
- R.L. Graham, 'Bounds on Multiprocessing Anomalies,' SIAM Journal of Applied Mathematics, Volume 17, pp.416-429, 1969 https://doi.org/10.1137/0117039
- E.G. Coffman Jr., M.R. Garey, D.S. Johnson, 'An Application of Bin-Packing to Multiprocessor Scheduling,' SIAM Journal of Computing, Volume 7, Number 1, pp.1-17, 1978 https://doi.org/10.1137/0207001
- Lee, C.Y., D. Massey, 'Multiprocessor Scheduling: Combining LFT and Multifit,' Discrete Applied Mathematics, Volume 20, PP.233-242, 1988 https://doi.org/10.1016/0166-218X(88)90079-0
- H. Chao, M. P. Harper, R. W. Quong, 'A Tighter Lower Bound for Optimal Bin Packing,' Operations Research Letters, Volume 18, pp.133-138, 1995 https://doi.org/10.1016/0167-6377(95)00041-0