ETRI Journal

Electronics and Telecommunications Research Institute (한국전자통신연구원)
권호 표지

A Low Power 16-Bit RISC Microprocessor Using ECRL Circuits

  • Shin, Young-Joon (Department of Electronic Engineering, Soongsil University) ;
  • Lee, Chan-Ho (Department of Electronic Engineering, Soongsil University) ;
  • Moon, Yong (Department of Electronic Engineering, Soongsil University)
  • Received : 2004.02.13
  • Published : 2004.12.31
Download PDF
⟨ Previous Next ⟩

Abstract

This paper presents a low power 16-bit adiabatic reduced instruction set computer (RISC) microprocessor with efficient charge recovery logic (ECRL) registers. The processor consists of registers, a control block, a register file, a program counter, and an arithmetic and logical unit (ALU). Adiabatic circuits based on ECRL are designed using a $0.35{\mu}m$ CMOS technology. An adiabatic latch based on ECRL is proposed for signal interfaces for the first time, and an efficient four-phase supply clock generator is designed to provide power for the adiabatic processor. A static CMOS processor with the same architecture is designed to compare the energy consumption of adiabatic and non-adiabatic microprocessors. Simulation results show that the power consumption of the adiabatic microprocessor is about 1/3 compared to that of the static CMOS microprocessor.

Keywords

References

  1. IEEE Symp. Low Power Electronics A Review of Adiabatic Computing Denker, J.S.
  2. Symp. VLSI Circuits Dig. of Tech. Papers Adiabatic Computing with the 2N-2N2D Logic Family Kramer, A.;Denker, J.S.;Avery, S.C.;Dickinson, A.G.;Wik, T.R.
  3. Symp. VLSI Circuits Power Dissipation Measurements on Recovered Energy Logic Hinman, R.T.;Schlecht, M.F.
  4. IEEE J. Solid State Circuits v.30 Adiabatic Dynamic Logic Dickinson, A.G.;Denker, J.S.
  5. Electric Lett. v.36 no.16 Low-Power Adiabatic Computing with NMOS Energy Recovery Logic Kim, C.W.;Yoo, S.M.;Kang, M.S.
  6. IEEE Proc. v.148 Adiabatic Carry Look-Ahead Adder with Efficient Power Clock Generator Mahmoodi-Meinnand, H.;Afzali-Kusha, A.;Nourani, M.
  7. IEEE Proc. Southeastcon An Efficient Adiabatic Charge-Recovery Logic Varga, L.;Kovacs, F.;Hosszu, G.
  8. IEEE J. Solid State Circuits v.31 no.4 An Efficient Charge Recovery Logic Circuit Moon, Y.;Jeong, D.K.
  9. IEEE Trans. Computers v.C-31 no.3 A Regular Layout for Parallel Adders Brent, R.;Kung, H.T.
  10. Digital Integrated Circuits Rabaey, Jan M.
  11. Electronics Lett. v.34 no.4 Reversible Energy Recovery Logic Circuit without Non-adiabatic Energy Loss Lim, Joon-Ho;Kwon, Ki-Paek;Chae, Soo-Ik
  12. ITC-CSCC 2002 A 16-Bit Adiabatic Macro Blocks with Supply Clock Generator for Micro-Power RISC Datapath Lee, H.S.;Na, I.H.;Leem, C.;Moon, Y.
  13. ETRI J. v.25 no.5 AE32000B: a Fully Synthesizable 32-Bit Embedded Microprocessor Core Kim, Hyun-Gyu;Jung, Dae-Young;Jung, Hyun-Sup;Chio, Young-Min;Han, Jung-Su;Min, Byung-Gueon;Oh, Hyeong-Cheol
  14. ETRI J. v.22 no.4 On-chip Multiprocessor with Simultaneous Multithreading Park, Kyoung;Choi, Sung-Hoon;Chung, Yong-Wha;Hahn, Woo-Jong;Yoon, Suk-Han