The Transactions of the Korean Institute of Electrical Engineers P (전기학회논문지P)
- Volume 52 Issue 4
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- Pages.172-178
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- 2003
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- 1229-800X(pISSN)
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- 2586-7792(eISSN)
Design of Parameters for High Power Static Var Compensator Used Cascade Multilevel Inverter
직렬형 멀티레벨 인버터를 사용한 대용량 무효전력 보상장치의 파라메타 설계
- Received : 2003.07.30
- Accepted : 2003.09.02
- Published : 2003.12.01
Abstract
This paper examines the application of high voltage static var compensator(SVC) with cascade multilevel inverter which employs H-bridge inverter(HBI). This method has the primary advantage that the number of voltage levels can be increased for a given number of semiconductor devices when compared to the conventional control methods. The SVC system is modeled using the d-q transform which calculates the instantaneous reactive power. This model is used to design a controller and analyze the SVC system. From the mathematical model of the system, the design procedures of the circuit parameters L and C are presented in this thesis. To meet the specific total harmonic distortion(THD) and ripple factor of the capacitor voltage, the circuit parameters L and C are designed. Simulated and experimental results are also presented and discussed to validate the proposed schemes.