JSTS:Journal of Semiconductor Technology and Science

  • 제3권4호
  • /
  • Pages.194-198
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  • 2003
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  • 1598-1657(pISSN)
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  • 2233-4866(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
권호 표지

A design of 16-bit adiabatic Microprocessor core

  • Youngjoon Shin (School of Electronic Engineering, Soongsil University) ;
  • Lee, Hanseung (School of Electronic Engineering, Soongsil University) ;
  • Yong Moon (School of Electronic Engineering, Soongsil University) ;
  • Lee, Chanho (School of Electronic Engineering, Soongsil University)
  • 발행 : 2003.12.01
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초록

A 16-bit adiabatic low-power Micro-processor core is designed. The processor consists of control block, multi-port register file and ALU. A simplified four-phase clock generator is designed to provide supply clocks for adiabatic processor. All the clock line charge on the capacitive interconnections is recovered to recycle the energy. Adiabatic circuits are designed based on ECRL(efficient charge recovery logic) and $0.35\mu\textrm$ CMOS technology is used. Simulation results show that the power consumption of the adiabatic Microprocessor core is reduced by a factor of 2.9~3.1 compared to that of conventional CMOS Microprocessor

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참고문헌

  1. J. S. Denker, 'A review of adiabatic computing,' IEEE Symp. on Low Power Electronics, pp. 94-97, 1994 https://doi.org/10.1109/LPE.1994.573218
  2. A. Kramer, J. S. Denker, S. C. Avery, A. G. Dickinson and T. R. Wik, 'Adiabatic computing with the 2N-2N2D logic family,' in Symp. on VLSI Circuits Dig. of Tech Papers, pp. 25 -26, 1994
  3. R. T. Hinman and M. F. Schlecht, 'Power dissipation measurements on recovered energy logic,' in Symp. on VLSI Circuits, pp. 19 - 20, 1994
  4. A. G. Dickinson and J. S. Denker, 'Adiabatic dynamic logic,' JSSC, vol. 30, pp. 311 - 315, 1995 https://doi.org/10.1109/4.364447
  5. C. W. Kim, S. M. Yoo and M. S. Kang, 'Low-power adiabatic computing with NMOS energy recovery logic,' electric letters, vol.36, no.13, pp. 1349-1350, Aug. 2000 https://doi.org/10.1049/el:20000962
  6. H. Mahmoodi-Meinnand, A. Afzali-Kusha and M. Nourani, 'Adiabatic carry look-ahead adder with efficient power clock generator,' lEE Proc., vol.148, pp. 229-234, Oct. 2001 https://doi.org/10.1049/ip-cds:20010439
  7. L. Varga, F. Kovacs and G. Hosszu, 'An efficient adiabatic charge-recovery logic,' IEEE proc. southeastcon, pp. 17 - 20, 2001 https://doi.org/10.1109/SECON.2001.923080
  8. Y. Moon and D. K. Jeong, 'An efficient charge recovery logic circuit,' IEEE JSSC, vol.31, No.4, pp. 514-522, Apr. 1996 https://doi.org/10.1109/4.499727
  9. R. Brent and H.T. Kung, 'A regular layout for parallel adders,' IEEE trans. on Computers, vol. C-31, no. 3, pp. 260-264, Mar. 1982 https://doi.org/10.1109/TC.1982.1675982
  10. Jan M, Rabaey 'Digital Integrated Circuits' Prentice Hall Electronics and VLSI series, 1996
  11. Joonho Lim; Kipaek kwon; Soo-Ik Chae 'Reversible energy recovery logic circuit without non-adiabatic energy loss' Electronics Letters, Vol:34 Issue:4, pp. 344-346, 19 Feb. 1998 https://doi.org/10.1049/el:19980261