한국정보통신학회논문지 (Journal of the Korea Institute of Information and Communication Engineering)

  • 제7권7호
  • /
  • Pages.1478-1482
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  • 2003
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  • 2234-4772(pISSN)
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  • 2288-4165(eISSN)
한국정보통신학회 (The Korea Institute of Information and Commucation Engineering)
권호 표지

AES-128 Rijndael 암ㆍ복호 알고리듬의 설계 및 구현

The Design and Implementation of AES-128 Rijndael Cipher Algorithm

  • 신성호 (한밭대학교 대학원 컴퓨터공학과) ;
  • 이재흥 (한밭대학교 정보통신ㆍ컴퓨터공학부)
  • 발행 : 2003.12.01
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초록

In this paper. Rijndael cipher algorithm is implemented by a hardware. It was selected as the AES(Advanced Encryption Standard) by NIST. It has structure that round operation divided into 2 subrounds and subrounds are pipelined to calculate efficiently. It takes 5 clocks for one-round. The AES-128 cipher algorithm is implemented for hardware by ALTERA FPGA, and, analyzed the performance. The AES-128 cipher algorithm has approximately 424 Mbps encryption rate for 166Mhz max clock frequency. In case of decryption, it has 363 Mbps decryption rate fu 142Mhz max clock frequency. In case of cipher core, it has 320Mbps encryptionㆍdecryption rate for 125Mhz max clock frequency.

키워드

참고문헌

  1. J. Nechvatal, E. Barker, L. Bassham, 'Report on the Development of the Advanced Encryption Standard', NIST, 2000
  2. B. Weeks, M. Bean, 'Hardware Performance Simulation of Round 2 AES Algorithms', Third AES candidate Conference, 2000
  3. NIST, 'Announcing the Advanced Encryption Standard(AES)', FIPS PUB 197, 2001
  4. Viktor Fischer, 'Realization of the Round 2 AES Candidate using Altera FPGA', http:// www.nist.gov/aes