Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Design of the Charge pump PLL using Dual PFD

듀얼 위상 주파수 검출기를 이용한 차지펌프 PLL 설계

  • Lee, Jun-Ho (LG Electronics) ;
  • Lee, Geun-Ho (Kunsan National University, School of Electronic & Information Engineering) ;
  • Son, Ju-Ho (Dept. of Electrical Engineering, Chonbuk National University) ;
  • Kim, Sun-Hong (Dept. of Electrical Engineering, Chonbuk National University) ;
  • Yu, Young-Gyu (PLANET System) ;
  • Kim, Dong-Yong (Dept. of Electrical Engineering, Chonbuk National University)
  • 이준호 (LG電子) ;
  • 이근호 (群山大學校 電子情報工學部) ;
  • 손주호 (全北大學校 電氣電子工學科) ;
  • 김선홍 (全北大學校 電氣電子工學科) ;
  • 유영규 ((주)플레넷 中央硏究所) ;
  • 김동용 (全北大學校 電氣電子工學科)
  • Published : 2001.08.01
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Abstract

In this paper, the charge pump PLL using the dual PFD to improve the trade-off between acquisition behavior and locked behavior is proposed. This dual PFD consists of a positive edge triggered PFD and a negative edge triggered PFD. The proposed charge pump shows that it is possible to overcome the issue of the charge pump current imsmatch by the current subtraction circuit. Also, this charge pump can suppress reference spurs and disturbance of the VCO control voltage. The proposed charge pump PLL is simulated by SPICE using 0.25${\mu}m$ CMOS process parameters.

본 논문에서는 위상획득과정과 동기과정에서의 trade-off를 향상시킨 듀얼 위상 주파수 검출기를 이용하여 차지펌프 PLL을 설계하였다. 제안된 듀얼 위상 주파수 검출기는 상승에지에서 동작하는 POSITIVE 위상 주파수 검출기와 하강에지에서 동작하는 NEGATIVE 위상 주파수 검출기로 구성되어있다. 또한 PLL에 사용된 차지펌프는 전류뺄셈회로를 이용하여 전류 부정합을 감소시켰으며, reference spurs와 전압제어발진기의 변동을 감소시킬수 있도록 구현하였다. 제안된 PLL의 동작특성은 0.25${\mu}m$ CMOS 공종 파라미터를 이용하여 SPICE 시뮬레이션을 통해 검증되었다.

Keywords

References

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