The Transactions of the Korean Institute of Electrical Engineers D (대한전기학회논문지:시스템및제어부문D)

The Korean Institute of Electrical Engineers (대한전기학회)
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An ASIC Implementation of Synchronized Phasor Measurement Unit based on Sliding-DFT

순환 DFT에 기초한 동기 위상 측정 장치의 ASIC 구현

  • 김종윤 (중앙대 전자전기공학부) ;
  • 장태규 (중앙대 전자전기공학부) ;
  • 김재화 (삼성전자(주) 디지털미디어 총괄 중앙연구소)
  • Published : 2001.12.01
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Abstract

This paper presents an implementation method of multi-channel synchronized phasor measurement device, which is based on the ASIC implementation of the sliding-DFT. A time-shared multiplier structure is proposed to minimize the number of gates required for the implementation. The design is verified by the timing simulation of its operation. The effect of coefficient approximation in the recursive implementation of the sliding-DFT is analytically derived and verified with the computer simulations.

Keywords

References

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