Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Designing Modulo $({2^n}-1)$ Parallel Multipliers and its Technological Application Using Op Amp Circuits

Op Amp 회로를 이용한, 모듈로 $({2^n}-1)$ 병렬 승산기의 설계 및 그 기술의 응용

  • 이훈규 (광운대학교 ISRC) ;
  • 김철 (광운대학교 수학과 ISRC)
  • Published : 2001.06.01
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Abstract

In this paper, we introduce modulo ( 2$^n$-1) parallel-processing residue multipliers, using Op Amp circuits, and their technological application to designing binary multipliers. The limit of multiplying speed in computational processing is a serious harrier in the advances of VLSI technology. To solve this problem, we implement a class of modulo ( 2$^n$-1) parallel multipliers having superior time complexity to O( log$_2$( log$_2$( log$_2$$^n$))) by applying Op Amp circuits, while investigating their technological application to binary multipliers. Since they have excellent time & area complexity compared with previous parallel multipliers, and are applicable to designing binary multipliers of the same efficiency, such parallel multipliers possess high academic value. Indexing Terms Modular Multipliers. Binary Multipliers. Parallel Processing, Operational Amplifiers, Mersenne Numbers.

본 논문은, Op Amp 회로를 이용한, 모듈로(modulo) (2ⁿ-1) 병렬처리(parallel-processing) 잉여(residue) 승산기(multipliers)의 설계 및 이진(binary) 승산기 설계에 대한 그 기술의 응용 방법에 관한 것이다. 전산처리에 있어서 승산속도의 제약은 집적회로(VLSI) 기술의 발전에 많은 지장을 초래한다. 본 연구는, 이러한 문제를 해결키 위해 (Op Amp 회로를 이용) 모듈로 (2ⁿ-1) 상에서, 시간복잡도(time complexity)가 O( log₂( log₂( log₂ⁿ)))보다 우수한, 일종의 모듈로 병렬 승산기를 구현함과 동시에, 그 기술의 이진 승산기 설계에 대한 응용방법을 모색한다. 이러한 병렬 승산기는 기존의 병렬 승산기들에 비해 에어리어복잡도 (area complexity) 및 시간복잡도(time complexity)에 있어 매우 우수한 성질들을 갖게 되며, 같은 효율을 갖는 이진 승산기의 제작에 쉽게 응용할 수 있어 그 학술적 이용 가치가 높다.

Keywords

References

  1. R. E. Bryant, 'Graph-Based Algorithms for Boolean Function Manipulation,' IEEE Transactions On Computers, vol. 35, no. 8, pp. 677-691, Aug. 1986 https://doi.org/10.1109/TC.1986.1676819
  2. C. S. Wallace, 'A Suggestion for a Fast Multiplier,' IEEE Transactions On Electronic Computers, vol. 13, pp. 14-17, Feb. 1964 https://doi.org/10.1109/PGEC.1964.263829
  3. N. Takagi, H. Yasuura, and S. Yajima, 'High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree,' IEEE Transactions On Computers, vol. 34, no. 9, pp. 789-796, Sept. 1985 https://doi.org/10.1109/TC.1985.1676634
  4. F. J. Taylor, 'Large Moduli Multipliers for Signal Processing,' IEEE Transactions On Circuits and Systems, vol. 28, no. 7, pp. 731-736, July 1981 https://doi.org/10.1109/TCS.1981.1085027
  5. B. P. Sinha, and P. K. Srimani, 'Fast Parallel Algorithms for Binary multiplication and Their Implementation on Systolic Architectures,' IEEE Transactions On Computers, vol. 38, no. 3, pp. 424-431, Mar. 1989 https://doi.org/10.1109/12.21128
  6. A. Hiasat, 'New Memoryless, mod ($2^n{\pm}1$) Residue Multiplier,' Electronics Letters, vol. 28, no. 3, pp. 314-315, Jan. 1992 https://doi.org/10.1049/el:19920194
  7. A. A. Hiasat, 'New Efficient Structure for a Modular Multiplier for RNS,' IEEE Transactions On Computers, vol. 49, no. 2, pp. 170-174, Febr. 2000 https://doi.org/10.1109/12.833113
  8. E. D. Di Claudio, F. Piazza, and G. Orlandi, 'Fast Combinational Processors for DSP Applications,' IEEE Transactions On Computers, vol. 44, no. 5, pp. 624 -633, May 1995 https://doi.org/10.1109/12.381948
  9. A. Saed, M. Ahmadi, and G. A. Jullien, 'Analog Digits: Bit Level Redundancy in a Binary Multiplier,' IEL Data Base(0-7803-5148-7/98/$10.00c1998 IEEE), pp. 236-240, 1998 https://doi.org/10.1109/ACSSC.1998.750861
  10. J. B. Shin, J. K. Kim, and H. L. Kwang, 'Optimisation of Montgomery Modular Multiplication Algorithm for Systolic Arrays,' Electronics Letters, vol. 34, no. 19, pp. 1830-1831, Sept. 1998 https://doi.org/10.1049/el:19981299
  11. C. Efstathiou, D. Nikolos, and J. Kalamatianos, 'Area-Time Efficient Modulo $2^n-1$ Adder Design,' IEEE Transactions On Circuits and Systems-II: Analog and Digital Signal Processing, vol. 41, no. 7, pp. 463-467, July 1994 https://doi.org/10.1109/82.298378
  12. R. F. Coughlin and F. F. Driscoll, Operational-Amplifiers & Linear Integrated Circuits, Prentice Hall, pp. 434-436, 1998
  13. T. L. Floyd, Digital Logic Fundamentals, C. E. Merrill Publishing Company, pp. 205-212, 1977
  14. C. D. Walter, 'Systolic Modular Multiplication,' IEEE Transactions On Computers, vol. 42, no. 3, pp. 376 - 378, Mar. 1993 https://doi.org/10.1109/12.210181
  15. B. Arazi, 'Digital Signature Device,' US Patent, #5448639, 1995
  16. 김 광조, 김 철 '정보보호 이론의 발전,' 전자공학회지, 제 21권 5호, pp. 443-456, 1994년 5월