References
- J. P. Roth, 'Diagnosis of Automata Failures: A Calculus and a Method,' IBM Journal of Research and Development, vol. 10, pp. 278-291, July 1966
- P. Gael, 'An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits,' IEEE Trans. on Computer, vol. C-30, pp. 215-222, Mar. 1981 https://doi.org/10.1109/TC.1981.1675757
- H. Fujiwara, and T. Shimono, 'On the Acceleration of Test Generation Algorithms,' IEEE Trans. on Computer, vol. C-32, pp. 1137-1144, Dec. 1983 https://doi.org/10.1109/TC.1983.1676174
- M. Schultz, E. Trischler, and T. Sarfert, 'SOCRATES: A Highly Efficient Automatic Test Pattern Generatio System,' IEEE Trans. on CAD, pp. 126-137, Jan. 1988 https://doi.org/10.1109/43.3140
- Y. Matsunaga, 'MINT-An exact algorithm for finding minimum test sets,' IEICE Trans. Fundamentals, vol. E-76-A, pp. 1652-1658, Oct. 1993
- S. B. Akers, C. Joseph, and B. Krishnamurthy, 'On the role of independent fault sets in the generation of minimal test sets,' Proc. of International Test Conference, Sept. 1987, pp. 1100-1107
- B. Krishnamurthy, and S. B. Akers, 'On the complexity of estimating the size of test set,' IEEE Trans. on Computer, vol. C-33, no. 8, pp. 750-753, Aug. 1984
- B. Ayari, and B. Kaminska, 'A new dynamic test vector compaction for automatic test generation,' IEEE Trans. on CAD, vol. C-13, no. 3, pp. 353-358, Mar. 1994 https://doi.org/10.1109/43.265676
- S. Kajihara, I. Pomeranz, K Kinoshita, and S. M. Reddy, 'Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits,' Proc. of 30th Design Aturnation Conference, pp. 102-100, June 1993 https://doi.org/10.1145/157485.164617
- F. Brglez, and H. Fujiwara, 'A Neural Netlist of 10 Combinational Benchmark Designs and a Special Translator in Fortran,' Proc. of International Symposium on Circuits and Systems, June 1985
- F. Brglez, D. Bryan, and K. Kozminski, 'Combinational Profiles of Sequential Benchmark Circuits,' Proc. of International Symposium on Circuits and Systems, May 1989 https://doi.org/10.1109/ISCAS.1989.100747
- Sang Yoon Han, Sungho Kang, 'Efficient Redundancy Identification for Test Pattern Generation,' Proc. of IEEE International ASIC conference, pp 52-56, Sep. 1997. pp 52-56, September 1997 https://doi.org/10.1109/ASIC.1997.616977
- 임동욱, 민형복, '검사 신호에 대한 저비용 압축,' 정보과학회 논문지(A), 제 25권, 제 11호, Nov. 1998