Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
권호 표지

Mixed-Mode Transient Analysis of HBM ESD Phenomena

HBM ESD 현상의 혼합모드 과도해석

  • Choe, Jin-Yeong (Dept. of Electronic Electrical and Computer Engineering, Hongik University) ;
  • Song, Gwang-Seop (Dept. of Electrical Engineering, Hongik University)
  • 최진영 (홍익대학교 전자전기컴퓨터공학부) ;
  • 송광섭 (홍익대학교 전기공학과)
  • Published : 2001.01.01
Download PDF
⟨ Previous Next ⟩

Abstract

Based on mixed-mode transient analyses utilizing a 2-dimensional device simulator, we have suggested the methodology to analyze the HBM ESD phenomena in CMOS chips utilizing NMOS transistors for ESD protection, and have analyzes the HBM discharge mechanisms in detail. Also the second breakdown characteristics in the protection device have been successfully simulated based on mixed-mode simulations, to explain the discharge mechanisms leading to device failure. To analyze the effects of the device structure changes on the discharge characteristics, we have compared the results of DC analyses and mixed-mode transient analyses, and have discussed about more robust designs of NMOS transistor structures against HBM ESD based on the analyses.

2차원 소자 시뮬레이터를 이용하는 혼합모드 과도해석을 통해, NMOS 트랜지스터를 ESD 보호용 소자로 사용하는 CMOS 칩에서의 HBM ESD 현상에 대한 과도해석 방법론을 제시하고 HBM 방전 미케니즘에 대해 상세히 분석하였고, 보호용 소자 내에서의 2차항복 현상을 성공적으로 시뮬레이션하여 소자 파괴에 이르는 미케니즘을 설명하였다., 보호용 소자 구조의 변화가 방전 특성에 미치는 영향을 조사하기 위해 DC 해석 결과와 혼합모드 과도해석 결과를 비교 분석하였고, 분석 결과를 근거로 하여 HBM ESD에 보다 견고한 보호용 소자의 구조 설계에 대해 논의하였다.

Keywords

References

  1. C. H Diaz, S. M. Kang, and C. Duvvury,'Modeling of electrical overstress in integrated circuit', Kluwer Academic Publishers, 1995
  2. A Amerasekera and C. Duwury, 'ESD in silicon integrated circuits', JOHN WILEY & SONS, 1995
  3. A Amerasekera, W. van den Abeelen, L. van Roozendaal, M. Hannemann, and P. Schofield, 'ESD failure modes: characterization, mechanisms, and process influences,' IEEE Trans. Electron Devices, vol. 39, no. 2, pp. 430-436, Feb. 1992 https://doi.org/10.1109/16.121703
  4. T. L. Polgreen and A. Chatterjee, 'Improving the ESD failure threshold of silicided nMOS output transistors by ensuring uniform current flow,' IEEE Trans. Electron Devices, vol. 39, no. 2, pp. 379-388, Feb. 1992 https://doi.org/10.1109/16.121697
  5. A Chatterjee and T. Polgreen, 'A low-voltage triggering SCR for on-chip ESD protection at output and input pads,' IEEE Electron Device Lett., vol. 12, no. 1, pp. 21-22, Jan. 1991 https://doi.org/10.1109/55.75685
  6. J. Z. Chen, A Amerasekera, and T. Vrotsos, 'Bipolar SCR ESD protection circuit for high speed submicron Bipolar/BiCMOS circuits,' IEDM Tech Digest, pp. 337-340, Washington, DC, U.S.A, Dec. 1995 https://doi.org/10.1109/IEDM.1995.499209
  7. K Mayaram, J.-H. Chern, L. Arledge, and P. Yang, 'Electrothermal simulation tools for analysis and design of ESD protection devices,' IEDM Tech. Digest, pp. 909-912, Washington, DC, U.S.A., Dec. 1991 https://doi.org/10.1109/IEDM.1991.235278
  8. A Chatterjee, T. Polgreen, and A Amerasekera, 'Design and simulation of a 4KV ESD protection circuit for a $0.8{\mu}m$ BiCMOS process,' IEDM Tech. Digest, pp. 913-916, Washington, DC, U.S.A, Dec. 1991
  9. A Amerasekera, A Amerasekera, and M.-C. Chang, 'Prediction of ESD robustness in a process using 2-D device simulations,' IEEE IRPS proceedings, pp. 161-167, Atlanta, U.S.A, Mar. 1993 https://doi.org/10.1109/RELPHY.1993.283329
  10. C. Diaz, C. Duwury, and S.-M. Kang, 'Studies of EOS susceptibility in 0.6 urn nMOS ESD I/O protection structures,' EOS/ESD Symposium Proceedings, pp. 83-91, Lake Buena Vista, USA, Sept. 1993
  11. A Stricker, D. Gloor, and W. Fichtner 'Layout optimization of an ESD-protection n-MOSFET by simulation and measurement,' EOS/ESD Symposium Proceedings, pp. 205-211, Phoenix, U.SA, Sept. 1995 https://doi.org/10.1109/EOSESD.1995.478286
  12. H. Brand and S. Selberherr, 'Two-dimensional simulation of thermal runaway in a nonplanar GTO-thyristor,' IEEE Trans. Electron Devices, vol. 42, no. 12, pp. 2137-2146, Dec. 1995 https://doi.org/10.1109/16.477772
  13. 최진영, 임주섭, '소자 시뮬레이션을 이용한 ESD 보호용 NMOS 트랜지스터의 항복 특성 분석', 전자공학회논문지, 제34권, D편, 제11호, pp. 37-47, 1997년 11월
  14. ATLASII Framework, Version 4.3.0.R, Silvaco International, 1997
  15. A Amerasekera, L. van Roozendaal, J. Bruines, and F. Kuper, 'Characterization and modeling of second breakdown in NMOST's for the extraction of ESD-related process and design parameters,' IEEE Trans. Electron Devices, vol. 38, no. 9, pp. 2161-2168, Sept. 1991 https://doi.org/10.1109/16.83744
  16. ML-STD-883C Method 3015.7, DOD, 1989
  17. B. Krabbenborg, R. Beltman, P. Wolbert, and T. Mouthaan 'Physics of electro-thermal effects in ESD protection devices,' EOS/ESD Symposium Proceedings, pp. 98-103, Las Vegas, USA, Sept. 1991
  18. C. Russ, H. Gieser, and K Verhaege, 'ESD protection elements during HBM stress tests -Further numerical and experimental results,' EOS/ESD Symposium Proceedings, pp. 96-105, Las Vegas, USA, Sept. 1994
  19. ATLASⅡ Framework, Version 4.3.0.R Silvaco International
  20. IEEE Trans. Electron Devices v.38 no.9 Characterization and modeling of second breakdown in NMOST's for the extraction of ESD-related process and design parameters A.Amerasekera;L.van Roozendaal;J.Bruines;F.Kuper
  21. MIL-STD-883C Method 3015.7
  22. EOS/ESD Symposium Proceedings Physics of electro-thermal effects in ESD protection devices B.Krabbenborg;R.Beltman;P.Wolbert;T.Mouthaan
  23. EOS/ESD Symposium Proceedings ESD protection elements during HBM stress tests-Further numerical and experimental results C.Russ;H.Gieser;K.Verhaege