대한전자공학회논문지SP (Journal of the Institute of Electronics Engineers of Korea SP)

대한전자공학회 (The Institute of Electronics and Information Engineers)
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시스톨릭 어레이에 기반한 SADCT의 효율적 VLSl 구조설계

Design of an Efficient VLSI Architecture of SADCT Based on Systolic Array

  • 강태준 (경북대학교 전자전기공학부) ;
  • 정의윤 (경북대학교 전자전기공학부) ;
  • 권순규 (경북대학교 전자전기공학부) ;
  • 하영호 (경북대학교 전자전기공학부)
  • Gang, Tae-Jun (School of Electronic & Electrical Engineering, Kyungpook National University) ;
  • Jeong, Ui-Yun (School of Electronic & Electrical Engineering, Kyungpook National University) ;
  • Gwon, Sun-Gyu (School of Electronic & Electrical Engineering, Kyungpook National University) ;
  • Ha, Yeong-Ho (School of Electronic & Electrical Engineering, Kyungpook National University)
  • 발행 : 2001.05.01
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초록

본 논문에서는 시스톨릭 어레이에 기반한 모양 적응적 이산 여현 변환(SADCT)의 효율적 VLSI 구조를 제안한다. 모양 적응적 이산 여현 변환은 이산 여현 변환과 달리 변환 크기가 각 블록에서의 객체의 모양에 따라 가변적이므로 기존의 시간 순환구조에서는 각 처리소자의 이용도와 처리속도가 모두 저하된다. 본 논문에서는 이러한 단점을 극복하기 위해 메모리를 필요로 하지 않는 시스톨릭 어레이에 기반한 구조를 제안한다. 제안된 구조에서는 1차원 SADCT를 연속적으로 수행함으로 처리속도를 향상시키고 첫 번째 열의 처리소자들을 마지막 열의 처리소자들과 연결하고, 입력 데이터는 각각의 재배열된 블록에서의 최대 데이터 크기에 따라 각 열에 병렬로 입력하여 처리소자의 이용도를 향상시켰다. 제안된 구조는 VHDL로 기술하고 MentorTM를 이용하여 기능검증을 수행하였다. 검증결과, 하드웨어 복잡도가 다소 증가하나, 처리속도는 기존의 방법에 비해 두 배정도 향상되었다.

In this paper, an efficient VLSI architecture of Shape Adaptive Discrete Cosine Transform(SADCT) based on systolic array is proposed. Since transform size in SADCT is varied according to the shape of object in each block, it are dropped that both usability of processing elements(PE´s) and throughput rate in time-recursive SADCT structure. To overcome these disadvantages, it is proposed that the architecture based on a systolic way structure which doesn´t need memory. In the proposed architecture, throughput rate is improved by consecutive processing of one-dimensional SADCT without memory and PE´s in the first column are connected to that in the last one for improvement of usability of PE. And input data are put into each column of PE in parallel according to the maximum data number in each rearranged block. The proposed architecture is described by VHDL. Also, its function is evaluated by MentorTM. Even though the hardware complexity is somewhat increased, the throughput rate is improved about twofold.

키워드

참고문헌

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