참고문헌
- T. Burd and R. Broderson. Processor design for portable systems. Journal of VLSI Signal Processing, Vol. 13, No.2, pp. 203-222, 1996 https://doi.org/10.1007/BF01130406
- T. Sakurai and A. Newton, Alpha-power law MOSFET model and its application to CMOS inverter delay and other formulas. IEEE Journal of Solid State Circuits, Vol. 25, No.2, pp. 584-594, 1990 https://doi.org/10.1109/4.52187
- F. Yao, A. Demers, and S. Shenker. A scheduling model for reduced CPU energy. In Proc. of the 36th Annual Symposium on Foundations of Computer Science, pp. 374-382, 1995 https://doi.org/10.1109/SFCS.1995.492493
- I. Hong, G. Qu, M. Potkonjak, and M. B. Srivastava. Synthesis techniques for low-power hard real-time systems on variable voltage processor. In Proc. of the 19th IEEE Real-Time Systems Symposium, pp. 178-187, 1998 https://doi.org/10.1109/REAL.1998.739744
- T. Okuma, T. Ishihara, and H. Yasuura. Real-time task scheduling for a variable voltage processor. In Proc. of the 72th International Symposium On System Synthesis, pp. 24-29, 1999 https://doi.org/10.1109/ISSS.1999.814256
- Y. Shin and K. Choi. Power conscious fixed priority scheduling for hard real-time systems. In Proc. of the 36th Design Automation Conference, pp. 134-139, 1999 https://doi.org/10.1145/309847.309901
- Y. Lee and C. M. Krishna. Voltage-clock scaling for low energy consumption in Teal-Lime embedded systems. In Proc. of the 6th International Conference on Real-Time Computing Systems and Applications, pp. 272-279, 1999 https://doi.org/10.1109/RTCSA.1999.811255
- S. Lee and T. Sakurai. Run-time voltage hopping for low-power real-time systems. In Proc. of the 37th Design Automation Conference, pp. 806-809, 2000 https://doi.org/10.1109/DAC.2000.855424
- T. Burd, T. Pering, A. Stratakos, and R Brodersen. A dynamic voltage scaled microprocessor system. In Proc. of IEEE International Solid-State Circuits Conference, pp. 294-295, 2000 https://doi.org/10.1109/ISSCC.2000.839787
- M. Fleischmann. Crusoe power management: reducing the operating power with LongRun. In Proc. of HotChips 12 Symposium, 2000
- C. A. Healy, D. B. Whalley, and M. G. Harmon. Integrating the timing analysis 01 pipelining and instruction caching. In Proc. of the 16th IEEE Real-Time Systems Symposium, pp. 288-297, 1995 https://doi.org/10.1109/REAL.1995.495218
- S.-S. Lim. Y. H. Bae, G. T. Jang, B.-D. Rhee, S. L. Min, C. Y. Park, H. Shin, K. Park, and C. S. Kim. An accurate worst case tinting analysis for RISC processors. IEEE Transactions on Software Engineering; Vol. 21, No.7, pp, 593-604, 1995 https://doi.org/10.1109/32.392980
- Y. S. Li, S. Malik, and A. Wolfe. Cache modeling [or real-time software: beyond direct mapped instruction caches. In Proc. of the 17th IEEE Real-Time Systems Symposium. pp. 254-263, 1996 https://doi.org/10.1109/REAL.1996.563722
- T. Ishihara and H. Yasuura, Voltage scheduling problem for dynamically variable voltage processors. In Proc. of International Symposium On Low Power Electronics and Design, pp. 197-202, 1998