Deriving a Distributed Asynchronous Control Unit through Automatic Derivation of Asynchronous Finite State Machines based on the Process-Oriented Method

프로세스 중심방식에 기반한 비동기식 유한상태기의 자동생성을 통한 분산 비동기식 제어부의 유도

  • Kim, Ui-Seok (Dept. of Information Communication Engineering, Gwangju Institute of Science and Technology) ;
  • Lee, Jeong-Geun (Dept. of Information Communication Engineering, Gwangju Institute of Science and Technology) ;
  • Lee, Dong-Ik (Dept. of Information Communication Engineering, Gwangju Institute of Science and Technology)
  • 김의석 (광주과학기술원 정보통신공학과) ;
  • 이정근 (광주과학기술원 정보통신공학과) ;
  • 이동익 (광주과학기술원 정보통신공학과)
  • Published : 2001.08.01

Abstract

본 논문에서는 비동기식 상위수준합성기 제작의 일환으로 효율적인 비동기식 제어부의 자동생성에 관한 방법을 제안한다. 제안된 방법은 목적시스템의 사양으로써 주어진 제어데이터흐름그래프로부터 일련의 체계적인 변환과정을 통하여, 제어부를 구성할 제어회로들에 대응하는 계층적으로 분할된 비동기식 유한상태기들의 집합을 유도한다. 유도된 비동기식 유한상태기들은 현존하는 비동기식 제어회로 합성기를 통하여 해저드 없는 비동기식 제어회로들로 합성되며, 이들은 상호간에 4단계 핸드셰이킹에 기반한 신호교환을 통하여 동작하면서 전체 시스템을 제어하는 계층적으로 분할된 비동기식 제어부를 구성한다. 획득한 제어부는 계층.분산적이며, 면적, 성능 및 합성시간의 측면에서 기존방식을 통하여 생성한 제어부에 비해 우월하다.

Keywords

References

  1. S. Hauck, 'Asynchronous Design Methodologies : an Overview,' Proceedings of the IEEE, vol.83, no.1, pp.69-93, 1995 https://doi.org/10.1109/5.362752
  2. E. M. Sentovich, K. J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P. R. Stephan, R. K. Brayton and A. Sangiovanni-Vincentelli, 'SIS : A System for Sequential Circuit Synthesis,' May 1992
  3. S. M. Nowick, 'Automatic Synthesis of Burst-Mode Asynchronous Controllers,' Ph. D. thesis, Stanford University, 1995
  4. J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno and A. Yakovlev, 'Petrify : a tool for manipulating concurrent specifications and synthesis of asynchronous controllers,' IEICE Transactions on Information and Systems, vol.E80-D, no.3, pp.315 -325, 1997
  5. E. Pastor, J. Cortadella, A. Kondratyev and O. Roig, 'Structural Methods for the Synthesis of Speed- Independent Circuits,' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.17, no.11, pp.1108 -1129, 1998 https://doi.org/10.1109/43.736185
  6. K. Y. Yun and D. L. Dill, 'Automatic Synthesis of Extended Burst-Mode Circuits: Part IT (Automatic Synthesis),' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.18, no.2, pp.118-132, 1999 https://doi.org/10.1109/43.743715
  7. D. D. Gajski, N. D. Dutt, A. C-H Wu and S. Y-L Lin, 'High-Level Synthesis : Introduction to Chip and System Design,' Kluwer Academic Publishers, 1991
  8. G. DeMicheli, 'Synthesis and Optimization of Digital Circuits,' McGraw-Hill, 1994
  9. J. Cortadella and R. M. Badia, 'An Asynchronous Architecture Model for Behavioral Synthesis,' In Proceedings of European Conference on Design Automation, Mar., pp.307-311, 1992
  10. R. M. Badia, J. Cortadella, E. Pastor and A. Pardo, 'A High-Level Synthesis System for Asynchronous Circuits,' Sixth International Workshop on High-Level Synthesis, Nov., pp. 87-94, 1992
  11. I. Blunno and L. Lavagno, 'Automated Synthesis of Micro-Pipelines from Behavioral Verilog HDL,' In Proceedings of Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems, Apr., pp.84-92, 2000
  12. K. V. Berkel, 'Handshake Circuits. An asynchronous architecture for VLSI programming,' International Series on Parallel Computation 5. Cambridge University Press, 1993
  13. T. Kolks, S. Vercauteren and B. Lin, 'Control Resynthesis for Control-Dominated Asynchronous Designs,' In Proceedings of Second International Symposium on Advanced Research in Asynchronous Circuits and Systems, Mar., pp.233-243, 1996
  14. M. A. Pena,J. Cortadella, 'Combining Process Algebras and Petri Nets for the Specification and Synthesis of Asynchronous Circuits,' In Proceedings of Second International Symposium on Advanced Research in Asynchronous Circuits and Systems, Mar., pp.222-232, 1996
  15. D. D. Gajski, J. Zhu and R. Domer, 'Essential Issues in Codesign,' In J. Staunstrup and W. Wolf, editor, Hardware/Software Co-Design Principles and Practice, pp.1-45, Kluwer Academic Publishers, 1997
  16. P. Siegel, G. De Micheli and D. Dill, 'Automatic Technology Mapping for Generalized Fundamental Mode Asynchronous Designs,' In Proceedings of the Design Automation Conference, June 1993
  17. K. Y. Yun, P. A. Beerel, V. Vakilotojar, A. E. Dooply and J. Arceo, 'The Design and Verification of A High-Performance Low-Control-Overhead Asynchronous Differential Equation Solver,' IEEE Trans. VLSI Systems, vol.6, no.4, pp.643-655, 1998 https://doi.org/10.1109/92.736138