References
-
Memory
$BistCore^{TM}$ User's Reference Manual, GeneSys TestWare, Revision 1.4, June, 1998 - Yeujian Wu and Sanjay Gupta, 'Built-In Self-Test for Multi-Port RAMs,' Asian Test Symposium, 1997 https://doi.org/10.1109/ATS.1997.643989
- 한재천, 양선웅, 진명구, 장훈, '내장된 이중포트 메모리의 효율적인 테스트 방법에 관한 연구', 전자공학회 논문지, 1999
- A. J. Goor, 'Port Interference Faults in Two-Port Memories,' International Test Conference, 1999 https://doi.org/10.1109/TEST.1999.805833
- A. Benso, S. D. Carlo and P. Prinetto, 'A Programmable BIST Architecture for Cluster of Multiple-Port SRAMs,' International Test Conference, 2000 https://doi.org/10.1109/TEST.2000.894249
- A. J. Goor, Testing Semiconductor Memories, John Wiley & Sons Ltd., 1991
- R. P. Treuer and V. K. Agarwal, 'Fault Location Algorithms for Repairable Embedded RAMs,' International Test Conference, 1993 https://doi.org/10.1109/TEST.1993.470619
- Pinamki Mazumder and Kanad Chakraborty, Testing and Testable Design of High-Density Random Access Memories, Kluwer Academic Publishers, 1996
- Tom Chen and Glen Sunada, 'A Self-Testing and Self-Repairing Structure for Ultra-Large Capacity Memories,' International Test Conference, 1992
- J. V. Sas, G. V. Wause, E. Huyskens and D. Rabaey, 'BIST for Embeded Static RAMs with Coverage Calculation,' International Test Conference, 1993 https://doi.org/10.1109/TEST.1993.470679
- V. G. Mikitjuk, V. N. Yarmolik and A. J. van de Goor, 'RAM Testing Algorithms for Detection Multiple Linked Faults,' International Test Conference, 1996 https://doi.org/10.1109/EDTC.1996.494337
- M. Sachdev, 'Test and Testability Techniques for Open Defects in RAM Address Decoder,' International Test Conference, 1996 https://doi.org/10.1109/EDTC.1996.494336
- I. Schanstra and A. J. van de Goor, 'Industrial Evaluation of Stress Combinations for March Tests applied to SRAMs,' International Test Conference, 1999 https://doi.org/10.1109/TEST.1999.805831