한국정보과학회논문지:시스템및이론 (Journal of KIISE:Computer Systems and Theory)

한국정보과학회 (Korean Institute of Information Scientists and Engineers)
권호 표지

조합논리회로를 위한 효율적인 테스트 컴팩션 알고리즘

Efficient Test Compaction Algorithms for Combinational Logic Circuits

  • 김윤홍 (상명대학교 컴퓨터정보통신공학부)
  • Kim, Yun-Hong (Dept.of Computer Information Communication Engineering, Sangmyung University)
  • 발행 : 2001.04.01
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⟨ 이전 논문 다음 논문 ⟩

초록

본 논문에서는 조합논리회로의 테스트 컴팩션을 위한 두 가지 효율적인 알고리즘을 제안한다. 제안된 알고리즘들은 각각 동적인 컴팩션 기법과 정적인 컴팩션 기법을 사용하고 있으며, 실험을 위해 기존의 ATPG시스템인 ATALANTA에 통합 구현하였다. ISCAS85와 ISCAS89(완전스캔 버전) 벤치마크 회로에 대한 실험에서 본 시스템은 기존에 발표된 다른 컴팩션 알고리즘에 비하여 보다 작은 테스트 집합을 보다 빠르게 생성하였으며, 실험 결과를 통하여 제안된 알고리즘들의 유효성을 입증할 수가 있었다.

키워드

참고문헌

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