Journal of KIEE

대한전기학회 (The Korean Institute of Electrical Engineers)
권호 표지

The Effect of Dielectric Thickness and Barrier Rib Height on Addressing Time of Coplanar ac PDP

  • Lee, Sung-Hyun (Department of Electrical Engineering, Pusan National University. Mt.30, Jang-jeon dong, Keun-Jeong Gu, Pusan National University. Mt.30, Jang-jeon dong, Keum-jeong Gu, Pusan, 609-735, South Korea.) ;
  • Kim, Young-Dae (Department of Electrical Engineering, Pusan National University. Mt.30, Jang-jeon dong, Keun-Jeong Gu, Pusan National University. Mt.30, Jang-jeon dong, Keum-jeong Gu, Pusan, 609-735, South Korea.) ;
  • Shin, Joong-Hong (Dept. of Electrical Engineering, Dong Eui University) ;
  • Cho, Jung-Soo (Department of Electrical Engineering, Pusan National University. Mt.30, Jang-jeon dong, Keun-Jeong Gu, Pusan National University. Mt.30, Jang-jeon dong, Keum-jeong Gu, Pusan, 609-735, South Korea.) ;
  • Park, Chung-Hoo (Department of Electrical Engineering, Pusan National University. Mt.30, Jang-jeon dong, Keun-Jeong Gu, Pusan National University. Mt.30, Jang-jeon dong, Keum-jeong Gu, Pusan, 609-735, South Korea.)
  • 발행 : 2001.03.01
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초록

The addressing time should be reduced by modifying cell structure and/or driving method in order to replace the dual scan system by single scan and increase the luminance in large ac plasma display panel(PDP). In this paper, the effects of the dielectric layer thickness and the barrier rib height on the addressing time of ac PDP are investigated. It is found out that the addressing time was decreased with decreasing thickness of dielectric layer on the front glass and thickness of white dielectric layer on the rear glass. The decreasing rate were 160ns/10${\mu}{\textrm}{m}$ and 270nsd/10${\mu}{\textrm}{m}$, respectively. Also in case of decreasing the height of barrier rib, addressing time was decreased at the rate of 550ns/10${\mu}m$.

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