참고문헌
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- Proc. of International Test Conference Gate Delay Fault Test Generation for Non-Scan Circuits Van,Brakel,G.(et al.)
- IEEE Trans. on CAD Delay-Fault Test Generation and Synthesis for Testability under a Standard Design Methodology K.T.Cheng;S.Devadas;K.Keutzer
- IEEE Design and Test Transition Fault Simulation J.Waicukauski;E.Lindbloom;B.Rosen;V.lyengar
- Proc. ICCAD An Automatic Test Pattern Generation for the Detection of Path Delay Fault S.Reddy;C.Lin;Patil
- Proc. of International Test Conference Model for Delay Faults Based upon Path Smith,G.L.
- Proc. of International Test Conference Statistical AC Test Coverage D.M.Wu;C.E.Radke;J.P.Roth
- Proc. of International Test Conference Efficient Test Coverage Determination for Delay Faults J.L.Cater;V.S.Iyengar;B.K.Rosen
- Proc. of International Test Conference Accurate Path Delay Fault Coverage is Feasible S.Tragoudas
- IEEE Trans, on Computer v.C-32 no.12 Defect Level as a Function of Fault Coverage T.W.Williams;N.C.Brown
- Proc. of European Test Conference(ETC) Defect Level as a Function of Fault Coverage and Yield F.Coris;S.Martino;T.W.Williams
- IEEE Design & Test of Computer A Statistical Model for Delay-Fault Testing Eun Sei Park;M.R.Mercer;T.W.Williams
- Proc. 20th Design Automation Conference Statistical Techniques of Testing Verification James,H.Shelly;David,R.Trayon
- Computer and Electrical Eng v.23 no.5 A Statical Methodology for Modeling and Analysis of Path Delay Faults in VLSI Circuits Mustapha Hamad;Sami Al-Arian;David Landis
- Proc. 22nd Design Automation conference Analysis of Timing Failure Due to Random AC Defects in VLSI Circuits Nandakumar,N.Tendolkar
- Proc.of International Test Conference Computation of Delay Defect and Delay Fault Probabilities Using a Statistical Timing Simulator Jacques Benkoski;Andrzej,J.Strojwas
- Random Processes for Electrical Engineering(Second Edition) Alberto Leon-Garcia