References
- IDDQ Testing for CMOS VLSI R.Rajsuman
- International Symposium on Fault-Tolerant Computing Challenges in fault detection J.A.Abraham
- 서울대학교 반도체공동연구소 연구보고서 기능테스트와 IDDQ 테스트를 위한 자체 점검 BIST 회로의 설계 전병실(외)
- PHD. Thesis. Department of Computer Science, State university of New York Evaluation selection and generation of IDDQ tests P.J.Thadikaran
- Proc. IEEE Int'l Conf Carafe: An inductive fault analysis tool for CMOS VLSI circuit A.Jee;F.J.Ferguson
- IEEE VLSI Test Symposium Genetic-algorithm based test generation for current testing of bridging faults in CMOS VLSI circuits T.Lee;I.N.Hajj;E.M.Rudnick;J.H.Patel
- IEICE Trans. INF & SYST v.E81-D no.7 An iterative improvement method for generating compact tests for IDDQ testing of bridging faults T.Shinogi;T.Hayashi
- IEEE Trans. Computers v.45 no.10 Simulation and generation of IDDQ tests for bridging faults in combinational circuit S.Chakravarty;P.J.Thadikaran
- 한국통신학회논문지 v.24 no.12-A 합성고장을 위한 IDDQ 테스트 패턴 발생기의 구현 전병실(외)
- European DAC Test generation for IDDQ testing and leakage fault detection in CMOS circuits U.Mahlstedt(et al.)