References
- The International Technology Roadmap for Semiconductors
- Intl. Electron Devices Meeting Tech Digest A 0.05μm-CMOS with Ultra Shallow Source/Drain Junctions Fabricated by 5keV Ion Implantation and Rapid Thermal Annealing A.Hori;H.Nakaoka;H.Uminoto;K.Yamashita;M.Takase;N.Shimizu;B.Mizuno;S.Odanaka
- IEEE Trans. on Electron Devices v.42 no.10 A 40nm Gate Length n-MOSFET Mizuki Ono;Masanobu Saito;Takashi Yoshitomi;Claudio Fiegna;Tatsuya Ohguro;Hiroshi IWai
- Intl. Electron Devices Meeting Tech. Digest An SPDD p-MOSFET structure suitable for 0.1 and sub 0.1micron channel length and its electrical characteristics M.Saito;T.Yoshitomi;M.Ono;Y.Akasaka;H.Nii;S.Matsuda;H.S.Momose;Y.Katumata;Y.Ushiku;H.IWai
- Symp. on VLSI Tech. Plasma Doping of Boron for Fabricating the Surface Channel Sub-quarter micron PMOSFET B.Mizuno;M.Takase;I.Nakayama;M.Ogura
-
Intl. Electron Devices Meeting Tech. Digest
Novel Shallow Junction Technology using Decaborane(
$B_10H_14$ ) K.Goto;J.Matsuo;T.Sugii;H.Minakata;I.Yamada;T.Hisatsugu - IEEE Electron Device Lett. v.13 no.10 Ultra Shallow Junctions for ULSI Using As₂Implantation and Rapid Thermal Anneal B.G.Park;J.Bokor;H.S.Luftman;C.S.Rafferty;M.R.Pinto
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The 7th Korean Conference on Semiconductors
Sub 0.1μm NMOSFET with 12nm
$n^+$ -p Junction Using$As₂^+$ 5keV Ion Implantation B.Y.Choi;I.H.Nam;J.D.Lee;B.G.Park - J. of the Korean Phys. Society v.35 Realization of Ultra-Fine Lines Using Sidewall Structures and Their Application to nMOSFETs S.K.Sung;Y.J.Choi;J.D.Lee;B.G.Park
- Analysis and Design of MOSFETs: Modeling, Simulation, and Parameter Extraction J.J.Liou;A.Ortiz-Conde;F.Garcia-Sanchez
- MOSFET Models for VLSI Circuit Simulation-Theory and Practice N.Arora