Berlekamp-Massey 알고리즘을 이용한 소형 Reed-Solomon 디코우더의 아키텍쳐 설계

Architecture design of small Reed-Solomon decoder by Berlekamp-Massey algorithm

  • 전우형 (홍익대학교 대학원 전자공학과) ;
  • 송낙운 (홍익대학교 전자공학과)
  • 발행 : 2000.01.01

초록

본 논문에서는 소형 RS(Reed-Solomon) 디코우더의 효율적인 하드웨어 아키텍처를 제안하였다. 전체 아키텍쳐는 3단 파이프라인 구조를 택하였으며, 디코우딩 연산시, 에러위치다항식은 BMA(Berlekamp-Massey algortihm)에 의한 fast-iteration 방식으로 구하였으며, 계산의 복잡성이 요구도는 신드롬연산 부분은 ROM 테이블을 이용해서 병렬로 수행하고, 에러위치 다항식을 근을 구하는 부분은 Chein search 알고리즘을 응용한 방법을 ROM을 채택하여 계산하였다. 제안된 디코우더로 3심볼 랜덤에러정정을 수행하며, 시스템클록 25MHz를 사용하여 124Mbps의 디코우딩 데이터율을 가짐을 확인할 수 있었다.

In this paper, the efficient architecture of small Reed-solomon architecture is suggested. Here, 3-stage pipeline is adopted. In decoding, error-location polynomials are obtained by BMA using fast iteration method, and syndrome polynomials, where calculation complexity is required, are obtained by parallel calculation using ROM table, and the roots of error location polynomial are calculated by ROM table using Chein search algorithm. In the suggested decoder, it is confirmed that 3 symbol random errors can be corrected and 124Mbps decoding rate is obtained using 25 Mhz system clock.

키워드

참고문헌

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