입력신호 그룹화 방법에 의한 BIST의 테스트 시간 감소

Test Time Reduction of BIST by Primary Input Grouping Method

  • 장윤석 (光云大學校 電子材料工學科) ;
  • 김동욱 (光云大學校 電子材料工學科)
  • 발행 : 2000.08.01

초록

집적도 증가에 따라 비용이 증가하는 가장 대표적인 분야가 테스트 분야이며, 하드웨어 비용의 상대적인 감소에 따라 BIST 방법이 미래지향적 테스트 방법으로 지목받고 있다. 이 방법이 가지는 가장 큰 단점은 만족할 만한 고장검출률을 얻기 위해 필요한 테스트 시간의 증가이다. 본 논문에서는 BIST의 실현에 있어서 테스트 시간을 감소시키는 방안을 제안하였다. 이 방법은 입력의 그룹화와 테스트 포인트 삽입 방법을 사용하며, 테스트 포인트는 기존에 사용하던 것과는 다름 새로운 정의에 의해 결ㅈ어된다. 제안한 방법의 주요 알고리듬을 C-언어로 구현되었으며, 여러 가지 대상회로를 통해 실험한 결과 의사-무작위 패턴을 사용하는 경우에 비해 최대 $10^7$ 정도의 테스트 시간 감소를 가져올 수 있었으며, 고장검출률 또한 기존의 BIT방법보다 큰 것으로 확인되었다. 제안한 방법의 대상회로에 대한 상대적인 하드웨어 오버헤드는 대상회로가 커질수록 감소하고 지연시간 증가는 대형회로의 지연시간에 비해 미미한 것이어서, 대형회로를 BIST 방법에 의해 테스트할 때 제안한 방법이 매우 효과적일 것으로 사료된다.

The representative area among the ones whose cost increases as the integration ratio increases is the test area. As the relative cost of hardware decreases, the BIST method has been focued on as the future-oriented test method. The biggest drawback of it is the increasing test time to obtain the acceptable fault coverage. This paper proposed a BIST implementation method to reduce the test times. This method uses an input grouping and test point insertion method, in which the definition of test point is different from the previous one. That is, the test points are defined on the basis of the internal nodes which are the reference points of the input grouping and are merging points of the grouped signals. The main algorithms in the proposed method were implemented with C-language, and various circuits were used to apply the proposed method for experiment. The results showed that the test time could be reduced to at most $1/2^{40}$ of the pseudo-random pattern case and the fault coverage were also increased compared with the conventional BIST method. The relative hardware overhead of the proposed method to the circuit under test decreases as th e size of the circuit to be tested increases, and the delay overhead by the BIST utility is negligible compared to that of the original circuit. That means, the proposed method can be applied efficiently to large VLSI circuits.

키워드

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