네트워크-플로우 방법을 기반으로 한 통합적 데이터-경로 합성 알고리즘

Integrated Data Path Synthesis Algorithm based on Network-Flow Method

  • Kim, Tae-Hwan (Dept. of Computer Science, Korea Advanced Institute of Science and Technology)
  • 발행 : 2000.12.01

초록

이 논문은 상위 단계 데이터-경로 합성에서 연산 스케쥴링과 자원 할당 및 배정을 동시에 고려한 통합적 접근 방법을 제시한다. 제안한 방법은 스케쥴링 되어있지 않은 데이터-플로우 그래프에 대해서 수행에 필요한 총 clock 스텝 수와 필요한 회로 면적을 동시에 최소화하는 데이터-경로 생성에 특징이 있다. 일반적으로, 연결선의 결정이 합성의 마지막 단계에서 이루어지는 기존의 방법과는 다르게, 우리의 접근 방법은 연산 스케쥴링과 연산의 연산 모듈 배정 그리고 변수의 레지스터 배정 작업을 동시에 수행하여 추가적인 연결선의 수를 매 clock 스텝마다 최적화(optimal) 시킨다. 본 논문은, 이 문제를 최소-비용의 최대-플로우 문제로 변형하여 minimum cost augmentation 방법으로 polynomial time 안에 해결하는 알고리즘을 제안한다.

키워드

참고문헌

  1. D. Gajski, N. Dutt, A. Wu, and S. Lin (Eds.) High-level Synthesis - Introduction to Chip and System Design, Kulwer Academic Publishers, 1992
  2. C. Huang, Y. Chen, Y. Lin, and Y. Hsu, 'Data Path Allocation based on Bipartite Weighted Matching,' Proc. of Design Automation Conference, pp. 499-504, 1990 https://doi.org/10.1109/DAC.1990.114907
  3. C. Hwang J. Lee, and Y. Hsu, 'A Formal Approach to the Scheduling Problem in High Level Synthesis,' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 10. no. 4, pp,464-475, April 1991 https://doi.org/10.1109/43.75629
  4. B. Pangrle, 'Splicer: A Heuristic Approach to Connectivity Binding,' Proc. of Design Automation Conference, pp. 536-541, 1988 https://doi.org/10.1109/DAC.1988.14812
  5. S. Tarafdar, M. Leeser, 'The DT-Model: High-level Synthesis using Data Transfers,' Proc. of Design Automation Conference, pp. 114-117, 1998 https://doi.org/10.1145/277044.277069
  6. S. Tarafdar, M. Leeser, Z. Yin, 'Integrating Floorplanning in Data Transfer Based High-level Synthesis,' Proc. of International Conference on Computer-Aided Design, pp. 412-417, 1998 https://doi.org/10.1145/288548.289063
  7. M. Xu and F. Kurdahi, 'Layout-driven High-level Synthesis for FPGA Based Architectures,' Proc. of Design and Test Conference in Europe, 1998 https://doi.org/10.1109/DATE.1998.655896
  8. M. Balakrishnan and P. Marwedel, 'Integrated Scheduling and Binding: A Synthesis Approach for Design Space Exploration,' Proc. Design Automation Conference, pp. 68-74, 1989
  9. R. Cloutier and D. Thomas, 'The Combination of Scheduling, Allocation, and Mapping in a Single Algorithm,' Proc. Design Automation Conference, pp. 71-76, 1990 https://doi.org/10.1109/DAC.1990.114832
  10. P. Paulin and J. Knight, 'Scheduling and Binding Algorithms for High-Level Synthesis,' Proc. Design Automation Conference, pp. 1-6, 1989
  11. S. Devadas and A. Newton, 'Algorithm for Hardware Allocation in Data Path Synthesis,' IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems. vol. 8, no. 7, pp, 768-781, July, 1989 https://doi.org/10.1109/43.31534
  12. P. Kollig, B. AI-Hashimi, 'Simultaneous Scheduling, Allocation and Binding in High-level Synthesis,' Electronics Letters, vol. 33, no. 18, August 1997
  13. W, Dougherty and D. Thomas, 'Unifying Behavioral Synthesis and Physical Design,' Proc. of Design Automation Conference, pp. 756-761, 2000
  14. S. Hassoun, 'Fine Grained Incremental Rescheduling Via Architectural Retiming,' Proc. of International Symposium on System Synthesis, pp. 158-163, 1998 https://doi.org/10.1109/ISSS.1998.730619
  15. R. Tarjan, Data Structures and Network Algorithms, Society for Industrial and Applied Mathematics, 1983
  16. M. Rim et al. 'Optimal Allocation and Binding in High-Level Synthesis of VLSI Digital Systems,' Tech. Report, Dept. of Electrical and Computer Engineering, University of Wisconsin - Madison, Sept. 1991
  17. M. Rim et al. 'Optimal Allocation and Binding in High-Level Synthesis,' Proc. Design Automation Conference, pp. 120-123, 1992 https://doi.org/10.1109/DAC.1992.227850
  18. F. Tsai and Y. Hsu, 'STAR: An Automatic Data Path Allocator.' IEEE Trans, on Computer-Aided Design of Integrated Circuits and Systems, vol. 11. no. 9, pp, 1053-1064, Sept. 1992 https://doi.org/10.1109/43.159991