References
- Archibald, J. K. and Baer, J.-L., 'Cache coherence protocols: Evaluation using a multiprocessor simulation model,'ACM Trans. on Computer Systems, Vol.4, No.4, pp. 273-298, 1986 https://doi.org/10.1145/6513.6514
- Tomasevic, M. and Milutinovic, V., 'Hardware Approaches to Cache Coherence in Shared-Memory Multiprocessors: Part 1, ' IEEE Micro, vol. 14, no. 5, pp. 52-59, Oct. 1994 https://doi.org/10.1109/MM.1994.363067
- Tomasevic, M. and Milutinovic, V., 'Hardware Approaches to Cache Coherence in Shared-Memory Multiprocessors: Part 2,' IEEE Micro, vol. 14, no. 6, pp. 61-66, Dec. 1994 https://doi.org/10.1109/40.331392
- Censier, L. M. and Feautrier, P., 'A New Solution to Coherence Problems in Multicache Systems,' IEEE Trans. on Computers, Vol.C-27, No.12, pp. 1112-1118, 1978 https://doi.org/10.1109/TC.1978.1675013
- Agarwal, A., Simoni, R., Hennessy, J., and Horowitz, M., 'An Evaluation of Directory Schemes Cache Coherence,' in Proc. 15th Int'l Symposium on Computer Architecture, pp. 280-289, 1988 https://doi.org/10.1109/ISCA.1988.5238
- Gupta, A., Weber, W.-D., and Mowry, T., 'Reducing Memory and Traffic Requirements for Scalable Directory-Based Cache Coherence Schemes,' in Proc. 1990 Int'l Conference on Parallel Processing, pp. I.312-I.321, 1990
- Chaiken, D., Kubiatowicz, J., and Agarwal, A., 'LimitLESS Directories: A Scalable Cache Coherence Schemes,' in Proc. 4th Int'l Conference on Architectural Support for Programming Languages and Operating Systems, pp. 224-234, 1991 https://doi.org/10.1145/106972.106995
- James, D. V., Laundrie, A. T., Gjessing, S., and Sohi, G. S., 'Scalable Coherent Interface,' IEEE Computer, Vol.23, No.6, pp. 74-77, June 1990 https://doi.org/10.1109/2.55503
- Choi, J. H. and Park, K. H., 'Segment Directory : An Improvement to the Pointer in Directory Cache Coherence Schemes,' in Parallel Processing Letters, vol. 8, No. 4, pp. 577-588, Dec. 1998 https://doi.org/10.1142/S0129626498000572
- Choi, J. H. and Park, K. H., 'Segment Directory Enhancing the Limited Directory Cache Coherence Schemes,' in Proc. of the Merged Symposium of the 13th Int'l Parallel Processing Symposium & the 10th Symposium on Parallel and Distributed Processing, pp. 258-267, Apr. 1999
- Simoni, R., and Horowitz, M., 'Dynamic Pointer Allocation for Scalable Cache Coherence Directories,' in Proc. Int'l Symposium on Shared Memory Multiprocessing, pp. 72-81, 1991
- Agarwal, A., Bianchini, R., Chaiken, D., Johnson, K. L., Kranz, D., Kubiatowicz, J., Lim, B.-H., Mackenzie, K., and Yeung, D., 'The MIT Alewife machine : Architecture and performance,' in Proc. 22nd Annual Int'l Symposium on Computer Architecture, pp. 2-13, 1995 https://doi.org/10.1145/223982.223985
- Simoni, R., 'Cache Coherence Directories for Scalable Multiprocessors,' Ph. D. Thesis, Staford University, 1995
- Covington, R. G., Dwarkadas, J. R., Jump, J. R., Sinclair J. B., and Madala S., 'Efficient Simulation of Parallel Computer Systems,' Int. Journal in Computer Simulation, Vol. 1, No. 1, pp. 31-58, 1991
- Goldschmidt, S., 'Simulation of multiprocessors : Accuracy and performance,' Ph. D. Thesis, Stanford University, 1993
- Agarwal, A., 'Limits on Interconnection Network Performance,' IEEE Trans. on Parallel and Distributed Systems, Vol.2, No.4, pp. 398-412, 1991 https://doi.org/10.1109/71.97897
- Woo, S. C., Ohara, M., Torrie, E., Singh J. P., and Gupta, A., 'The SPLASH-2 Programs: Characterization and Methodological Considerations,' in Proc. 22nd Int'l Symposium on Computer Architecture, pp. 24-36, 1995
- Scheurich, C. and Dubois, M., 'Correct memory operation of cache-based multiprocessors,' in Proc. 14th Annual Int'l Symposium on Computer Architecture, pp. 234-243, 1987 https://doi.org/10.1145/30350.30377
- Kuskin, J., Ofelt, D., Heinrich, M., Heinlein, J., Simoni, R., Gharachorloo, K., Chapin, J., Nakahira, D., Baxter, J., Horowitz, M., Gupta, A., Rosenblum, M., and Hennessy, J., 'The Stanford FLASH Multiprocessor,' in Proc. 21st Annual Int'l Symposium on Computer Architecture, pp. 302-313, 1994 https://doi.org/10.1145/191995.192056