참고문헌
- D. Gajski, N. Dutt, A. Wu and S. Lin, High-Level Synthesis Introduction to Chip and System Design, Kulwer Academic Publishers, 1992
- C.-J. Tseng and D.P. Siewiorek, 'Automated Synthesis of Data Paths in Digital Systems.' IEEE Trans. on Computer-Aided Design, Vol. CAD-5, No. 3, pp. 379-395, July 1986
- P. Marwedel, 'The MIMOLA design system: Tools for the Design of Digital Processors,' Proc. Design Automation conference, pp. 587-593, 1984
- L. Stok, 'Interconnection Optimization During Data Path Allocation,' Proc. European Design Automation Conference, pp. 141-145, 1990 https://doi.org/10.1109/EDAC.1990.136635
- M. Balakrishnan et aI., 'Allocation of Mutiport Memories in Data Path Synthesis,' IEEE Trans, on Computer-Aided Design, Vol. 7, No.4, pp. 536-540, April 1988
- I. Ahmad and C. Y. Roger Chen, 'Post-Process for Data Path Synthesis using Multiport Memories,' Proc. International Conference on Computer-Aided Design, pp. 276-279, 1991
- P. R. Panda, N. Dutt, and A. Nicolau, 'Memory Issues in Embedded Systems-on-Chip: Optimizations and Exploration,' Kluwer Academic Publishers. Morwell, MA, 1999
- L. Ramachandran, D. D. Gajski, and V. Chaiyakul, 'An algorithm for Array Variable Clustering,' Proc. of European Design Automation conference, pp. 262-266. 1994 https://doi.org/10.1109/EDTC.1994.326867
- H. Schmit and D. E. Thomas, 'Synthesis of Application Specific Memory Designs,' IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 5, No. 3, pp. 101-111, March 1997 https://doi.org/10.1109/92.555990
- P. R. Panda, 'Memory Bank Customization and Assignment in Behavioral Synthesis,' Proc. International Conference on Computer-Aided Design, pp. 477-481, 1999
- F. J. Kurdahi and A. C. Parker, 'REAL: A Program for Register Allocation,' Proc. Design Automation Conference, pp. 80-85, 1987 https://doi.org/10.1145/37888.37920
- E. G. Coffman et aI., 'Approximation Algorithms for Bin Packing An Updated Survey' in Algorithm Design for Computer System Design, M. Luccertini, G. Ausiello and P. Serafiri, Springer Verlag, 1984
- M. R. Garey, R. L. Graham, D. S. Johnson and A. C. Yao, 'Resource Constrained Scheduling as Generalized Bin Packing,' J. combinatorial Theory, Ser. A21, pp. 257-298, 1976
- C. Y. Huang, Y. S. Chen, Y. L. Lin, Y. C. Hsu, 'Data Path Allocation Based on bipartite Weighted Matching,' Proc. Design Automation Conference, pp. 499-504, 1990 https://doi.org/10.1109/DAC.1990.114907
- C. A. Parpachristou and H. Konuk, 'A Linear Program Driven Scheduling and Allocation Method Followed by an Interconnection Optimization Algorithm,' Proc. Design Automation Conference, pp. 77-83, 1990 https://doi.org/10.1145/123186.123231
- P. G. Paulin and J. P. Knight, 'High-Level Synthesis Benchmark Results using a Global Scheduling Algorithm,' in Logic and Architecture Synthesis for Silicon Compilers, North-Holland, pp. 211-228, 1989
- F. S. Tsai and Y. C. Hsu, 'Data Path Construction and Refinement,' Proc. International Conference on Computer-AI\ided Design, pp. 308-311, 1990 https://doi.org/10.1109/ICCAD.1990.129910
- B. S. Haroun and M. I. Elmasry, 'Architecture Synthesis for DSP Silicon Compiler,' IEEE Trans. on Computer-Aided Design, Vol. CAD-8, No.4, pp. 431-447, April 1989