대한전기학회논문지:전기물성ㆍ응용부문C (The Transactions of the Korean Institute of Electrical Engineers C)

대한전기학회 (The Korean Institute of Electrical Engineers)
권호 표지

Gated Diode의 항복전압에 관한 해석적 표현

Analytical Expressions for the Breakdown Voltage of Gated Diodes

  • 발행 : 2000.05.01
PDF 다운로드
⟨ 이전 논문 다음 논문 ⟩

초록

Analytical expression for the breakdown voltage of the gated diodes were derived as f function of doping concentration and gate voltage, and verified by numerical simulations using ATLAS. The analytical results are in good agreement with simulation results within 5% error when the gate voltage changes from -50V to 130V in case of ND = $1\times1015 cm^{-3}$ and within 10% error when the doping concentration is changed from $5\times1014 cm^{-3}\; to\; 2\times1015 cm6{-3}$, respectively.

키워드

참고문헌

  1. S. Colak and E. Stupp, 'Reverse avalanche break down in gated diodes,' Solid St. Electronics, vol. 23, pp. 467-472, 1980 https://doi.org/10.1016/0038-1101(80)90083-0
  2. SILVACO. Two-dimensional device simulation program, user's manual. 1997
  3. W. Fulop, 'Calculation of avalanche breakdown of silicon P-N junctions,' Solid St. Electronics, vol. 10, pp. 39-43, 1967 https://doi.org/10.1016/0038-1101(67)90111-6
  4. B. Baliga and S. Ghandhi, 'Analytical solutions for the breakdown voltage of abrupt cylindrical and spherical junctions,' Solid St. Electronics, vol. 19, pp. 739-744, 1976 https://doi.org/10.1016/0038-1101(76)90152-0