ETRI Journal

Electronics and Telecommunications Research Institute (한국전자통신연구원)
권호 표지

On-Chip Multiprocessor with Simultaneous Multithreading

  • Received : 1999.08.11
  • Published : 2000.12.31
Download PDF
⟨ Previous Next ⟩

Abstract

As more transistors are integrated onto bigger die, an on-chip multiprocessor will become a promising alternative to the superscalar microprocessor that dominates today's microprocessor marketplace. This paper describes key parts of a new on-chip multiprocessor, called Raptor, which is composed of four 2-way superscalar processor cores and one graphic co-processor. To obtain performance characteristics of Raptor, a program-driven simulator and its programming environment were developed. The simulation results showed that Raptor can exploit thread level parallelism effectively and offer a promising architecture for future on-chip multi-processor designs.

Keywords

References

  1. Computer Architecture A Quantitative Approach Hennessy, John L.;Patterson, David A.
  2. Superscalar Microprocessor Design Johnson, Mike
  3. IEEE Micro v.16 no.6 The Microprocessor Today Slater, M.
  4. Limits of Instruction Level Parallelism , WRL Research Report 93/6 Wall, D.
  5. IEEE Computer v.31 no.1 Challenges and Trends in Processor Design Wilson, J.
  6. IEEE Micro v.17 no.5 Simultaneous Multithreading: A Platform for Next-Generation Processor Egger, S.(et al.)
  7. Proc. of Int'l Symp. on Computer Architecture Evaluation of Design Alternatives for Multiprocessor Microprocessor Nayfe, B.;Hammond, L.;Olukotun, K.
  8. IEEE Computer v.30 no.9 A Single-Chip Multiprocessor Hammond, L.(et al.)
  9. IEEE Micro v.16 no.3 Multiprocessors From a Software Perspective Amarashinhe, S.(et al.)
  10. IEEE Tr. on Parallel and Distributed Systems v.3 no.5 Performance Tradeoff in Multithreading Processors Agarwal, A.(et al.)
  11. Proc. of Int'l Conf. on Supercomputing The Tera Computer System Alverson, R.(et al.)
  12. Proc. of Symp. On Parallel Algorithms and Architectures Analysis of Multithreaded Architectures for Parallel Computing Saavedra, R.;Culler, D.;Eicken, T.
  13. Advances in Computers v.46 Multithreaded Systems Kavi, K.;Lee, B.;Hurson, A.
  14. Journal of Parallel and Distributed Computing v.40 Data and Workload Distribution in a Multithreaded Architecture Sohn, A.;Sato, M.;Yoo, N.;Gaudiot, J.
  15. Proc. of Int'l Symp. on Computer Architecture Improved multithreading techniques for hiding communication latency in multiprocessors Boothe, B.;Ranade, A.
  16. Programming with POSIX Threads Botenhof, D.
  17. Proc. of Int'l Symp. on Computer Architecture Very Long Instruction Word Architecture and the ELI-512 Fisher, J.
  18. The SPARC Architecture Manual SPARC International, Inc.
  19. UltraSPARC-I User's Manual SPARC Technology Business
  20. Computer Architecture News v.20 no.1 SPLASH: Stanford Parallel Applications for Shared Memory Singh, J.;Weber, W.;Gupta, A.
  21. Proc. of Int'l Conf. on Parallel and Distributed Computing Systems STAP Benchmark Evaluation of Three Massively Parallel Processors Wang, C.;Hwang, K.
  22. IPDPS 2000 Workshop, LNCS 1800 Performance of On-Chip Multiprocessors for Vision Tasks Chung, Y.(et al.)
  23. ETRI Journal v.20 no.4 Evaluation of Cluster-Based System for OLTP Application Hahn, Woo-Jong;Yoon, Suk-Han;Lee, Kwang-Woo;Dubois, Michel
  24. ETRI Journal v.20 no.4 An Asynchronous Algorithm for Balancing Unpredictable Workload on Distributed-Memory Machine Chung, Yong-Hwa;Park, Jin-Won;Yoon, Suk-Han