The Transactions of the Korean Institute of Electrical Engineers A (대한전기학회논문지:전력기술부문A)
- Volume 48 Issue 7
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- Pages.909-915
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- 1999
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- 1229-2443(pISSN)
Implementation of High-Speed Reed-Solomon Decoder Using the Modified Euclid's Algorithm
개선된 수정 유클리드 알고리듬을 이용한 고속의 Reed-Solomon 복호기의 설계
Abstract
In this paper, we propose an efficient VLSI architecture of Reed-Solomon(RS) decoder. To improve the speed. we develope an architecture featuring parallel and pipelined processing. To implement the parallel and pipelined processing architecture, we analyze the RS decoding algorithm and the honor's algorithm for parallel processing and we also modified the Euclid's algorithm to apply the efficient parallel structure in RS decoder. To show the proposed architecture, the performance of the proposed RS decoder is compared to Shao's and we obtain the 10 % efficiency in area and three times faster in speed when it's compared to Shao's time domain decoder. In addition, we implemented the proposed RS decoder with Altera FPGA Flex10K-50.