The Transactions of the Korean Institute of Electrical Engineers A (대한전기학회논문지:전력기술부문A)
- Volume 48 Issue 9
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- Pages.1161-1166
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- 1999
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- 1229-2443(pISSN)
New Scan Design for Delay Fault Testing of Sequential Circuits
순차 회로의 지연 고장 검출을 위한 새로운 스캔 설계
Abstract
Delay testing has become highlighted in the field of digital circuits as the speed and the density of the circuits improve greatly. However, delay faults in sequential circuits cannot be detected easily due to the existence of state registers. To overcome this difficulty a new scan filp-flop is devised which can be used for both stuck-at testing and delay testing. In addition, the new scan flip-flop can be applied to both the existing functional justification method and the newly-developed reverse functional justification method which uses scan flip-flops as storing the second test patterns rather than the first test patterns. Experimental results on ISCAS 89 benchmark circuits show that the number of testable paths can be increased by about 10% on the average.