Algorithm-based fault tolerant vector convolution on array processor

배열프로세서상에서 알고리즘 기반 결함허용 벡터 컨버루션

  • Published : 1998.08.01

Abstract

An algorithm-based fault tolerant scheme for the vector convolution is proposed employing the positive and negative checksum vectors that are defined in this paper based on the encoder vector. The proposed scheme is implemented on the aray processor, and then the amount of redundancy is examined thrugh the complexity analysis.

본 논문에서는 인코더 벡터(encoder vector)에 입각하여 양, 음 체크썸 벡터(positive, negative checksum vector)를 정의하고, 이를 벡터 컨버루션(vector convolution)에 적용하여 알고리즘 기반 결함허용 벡터 컨버루션 방식을 제안하였다. 또한 제안된 방식을 배열구조에서 구현하고 복잡도 해석을 통하여 추가 리던던시(redundancy)의 규모를 검토하였다.

Keywords

References

  1. Computer Architecture: A Modern Synthesis, Volume 2: Advanced Topics Subrata Dasgupta
  2. IEEE Trans. Comput. v.39 Algorithm based fault tolerance on a hypercube multiprocessor P. Banerjee;J. T. Rahmeh;C. Stunkel;V. S. Nair;K. Roy;V. Balasubramanian;J. A. Abraham
  3. Proc. IEEE v.66 Fault-tolerance: The Survival Attribute of Digital Systems A. Avizienis
  4. 'Quadded logi', in Redundancy Techniques for Computing Systems J. G. Tryon;Wilcox(ed.);Mann(ed.)
  5. IEEE Trans. Computers v.C-31 Concurrent Error Detection in ALUs by Recomputing with Shifted Operands J. H. Patel;L. Y. Fung
  6. IEEE Trans. Computers v.C-33 no.6 Algorithm-Based Fault Tolerance for Matrix Operations K. H. K. Huang;J. A. Abraham
  7. Proc. of 1993 International Symposium on Fault-Tolerant Computing: FTCS-23 Tolerance Determination for Algorithm-Based Checks Using Simplified Error Analysis Techniques A. Roy Chowdlhury;P. Banderjee
  8. Proc. of 1992 International Symposium on Fault-Tolerant Computing: FTCS-11 More Robust Tests in Algorithm-Based Fault-Tolerant Matrix Multiplication F. T. Assaas;S. Dutt
  9. Proc. 11th Int. Symp. Comput. Architect., Ann Arbor, MI Fault-secure algorithms for multiple processor systems P. Banerjee;J. A. Abraham
  10. Proc. Int. Symp. Fault-Tolerant Comput. General Linear Codes for Fault Tolerant Matrix Operations on Processor Arrays V. S. S. Nair;J. A. Abraham
  11. Analysis and Design of Parallel Algorithms S. Lakshmivarahan;S. K. Dhall
  12. Computer v.15 no.1 Why Systolic Aechitectures? H. T. Kung
  13. Computer System Science and Engineering v.7 no.3 Easily Testable and Reconfigurable Two-dimensional Systolic Arrays Kim, J. M.;S. M. Reddy
  14. VLSI Systems and Computations A Two-level Pipelined Systolic Array for Convolutions H. T. Kung;L. M. Ruane;D. W. L. Yen;H. T. Kung(ed.);R. F. Sproull(ed.);G. L. Steele, Jr.(ed.)