A new template matching algorithm and its ASIC chip implementation

Template matching을 위한 새로운 알고리즘 및 ASIC 칩 구현

This paper proposes a new template matching algorithm and its chip design. The CC and SAD algorithms require the massive amount of computation. Hence, several algorithms using quantization schemes have been proposed to reduce the amount of computation and its hardware cost. the proposed algorithm called the EMPPM improves at least 22% of the noise margin compared with the MPPM algorithm. In addition, the proposed architecture can reduce the gate count by more than 60% of that used in the SAD algorithm without usig quantization schemes and 28% of the MPPM algorithm. The VHDL models have been simulated by using the CADANCETEX>$^{TM}$ and logic synthesis has been performed by using the SYNOPSYSTEX>$^{TM}$ with $0.6\mu\textrm{m}$ SOG(sea-of-gate) cell library. The implemented chip consists of 35,829 gates, operates at 100 MHz (worst case 53 MHz) and performs the template maching with the speed of 200 Mpixels/sec.