전자공학회논문지C (Journal of the Korean Institute of Telematics and Electronics C)
- 제35C권8호
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- Pages.10-22
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- 1998
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- 1226-5853(pISSN)
병렬 테스트 방법을 적용한 고집적 SRAM을 위한 내장된 자체 테스트 기법
Built-in self test for high density SRAMs using parallel test methodology
초록
To handle the density increase of SRAMs, a new parallel testing methodology based on built-in self test (BIST) is developed, which allows to access multiple cells simultaneously. The main idea is that a march algorithm is dperformed concurently in each baisc marching block hwich makes up whole memory cell array. The new parallel access method is very efficient in speed and reuqires a very thny hardware overhead for BIST circuitry. Results show that the fault coverage of the applied march algorithm can be achieved with a lower complexity order. This new paralle testing algorithm tests an .root.n *.root.n SRAM which consists of .root.k * .root.k basic marching blocks in O(5*.root.k*(.root.k+.root.k)) test sequence.
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