Capacity Planning and Control of Probe Process in Semiconductor Manufacturing

반도체 Probe 공정에서의 생산 능력 계획

In semiconductor manufacturing, the probe process between fabrication and assembly process is constrained mostly by the equipment capacity because most products pass through the similar procedures. The probe process is usually performed in a batch mode with relatively short cycle times. The capability of the probe process can be determined by the optimal combination of the equipments and the products. A probe line usually has several types of equipment with different capacity. In this study, the probe line is modeled in terms of capacity to give the efficient planning and control procedure. For the practical usage, the hierarchical capacity planning procedure is used. First, a monthly capacity plan is made to meet the monthly production plan of each product. Secondly, the daily capacity planning is performed by considering the monthly capacity plan and the daily fabrication output. Simple heuristic algorithms for daily capacity planning are developed and some experimental results are shown.