알고리즘 및 아키텍쳐 수준 저전력 설계 자동화

  • Published : 1997.12.01

Abstract

Keywords

References

  1. Low-Power Portable Design Akira Matsuzawa
  2. Advanced RISC Machines Ltd. Fulbourn Road
  3. Design for testability of gated-clock FSMs European Design and test conference L. Benini;M. Favalli;G. De Micheli
  4. High Performance Design Automation for Multichip modules and packages J. D. Cho;P. Franzon
  5. 한국정보과학회 SIGTCS news v.7 no.2 Combinational Aspects of Lower Power Clock Networks in VLSI Circuits J. D. Cho
  6. 한국정보과학회 학술대회 데이터 전송시 스위칭 동작 회수의 최소화를 통한 전력소비 감축 및 압축률 개선 J. D. Cho;S. S. Chun
  7. 서울대학교 반도체 공동연구소 연구보고서, ISRC96-E-2020 소자의 스위칭 동작 최소화를 통한 디지탈 회로 저전력 상위 레벨 최적화에 관한 연구 J.D.Cho
  8. 대한전자공학회 학술대회 v.20 no.1 저전력 기술매핑을 위한 게이트 재합성 J. D. Cho;H.S.KIm
  9. IFIP Conf., on Parallel Processing Some Design Ideas for a VLIW Architecture for Sequential-Natured Software K. Ebcioglu
  10. Advanced Low-Power Digital Circuit Techniques M. Elrabaa;I. S. Abu-Khater;M. I. Elmasry
  11. Asynchronous Digital Circuit Design Computing without Clocks: Micropipelining the ARM processor S.B.Furber;G.Birtwistle, G.(eds.);A. Davis(eds.)
  12. Proc. of Int'l Symposium on Circuits and Systems Joint Scheduling and Allocation for Low Power Y.Fand;A.Albicki
  13. Proc. ICCD'94 The Design and Evaluation of an Asynchronous Microprocessor S.B.Furber;P. Day;J.D.Garside;N.C.Paver;J.V.Woods
  14. DAC A Programmable Power-Efficient Decimation Filter for Software Radios E. N. Farag;R. H. Yan;M. I. Elmsry
  15. International Symposium on Lower Power Electronics and Design Low Power Motion Estimation Design Using Adaptive Pixel Truncation Z.L.He;K.K. Chan;C. Y. Tsui;M. L. Liou
  16. VLSI Programming of Asynchronous Circuits for Low Power Kees van Berkel
  17. IEEE Design & Test of Computers Profile-Driven Behavioral Synthesis for Low Power VLSI Systems Nand Kumar;Srinivas Katkoori;Leo Rader;Ranga Vemuri
  18. Proceedings of the IEEE 1996 Custom Integrated Circuits Conference Implementing and Evaluating Adiabatic Arithmetic Units C. Knapp;P.J. Kindlmann;M.C. Papaefthymiou
  19. Scheduling techniques for reducing processor energy use in MacOS J. R. Lorch
  20. 1996 International Symposium on Low Power Electronics and Design Fixed-Phase Retiming for Low Power Design N. Lalgudi;M.C. Papaefthymiou
  21. Symp. on Low Power Electron Lower POwer Design of Memory Intensive applications-Case study : vector quanti-zation D. Lidsky;J. Rabaey
  22. IEEE Trans. on VLSI Systems v.3 no.2 Architectural Power Analysis : The Dual Bit Type Model P.Landman;J. Rabaey
  23. Proc. of the Int. Workshop on Power and Timing Modeling Optimization and Simulation (PATMOS) Low-Power Array Multipliers with Transition-Retaining Barriers Musoll;J. Cortadella
  24. International Symposium on Lower Power Electronics and Design Small Signal Model for Low Power DSP H. Mehta;B. M. Owens;M. J. Irwin
  25. ISSCC'96 A160㎒ 32b 0.5W CMOS RISC Microprocessor J. Montanaro(et al.)
  26. International Symposium on Lower Power Electronics and Design Dynamic Algorithm Transformation for Low Power Adaptive Filter M. Goel;N. Shanbhag
  27. IEEE Signal Pocessing Ⅷ Coefficient Optimization for Low Power Realization of FIR Filters M. Mehendale;S. D. Sherlekar;G. Venkatesh
  28. NATO ASI Series Low Power Design in Deep Submicron E;ectronics W. Nebel;J. Mermet
  29. Low Power Multiplication for FIR Filters C. J. Nocol;P. Larsson
  30. Proceedings of the IEEE v.77 Algorithm Transformation techniques for concurrent processors K.K.Parhi
  31. IEEE Trans. on Circuits and Systems-Ⅱ : Analog and Digital Signal Processing v.44 no.6 Algorithms for Low power and High Speed FIR Filter Realization Using Differential Coefficients N. Sankarayya;K. Roy;D. Bhattacharya
  32. Proc. of the IEEE/ACM International Conference on Computer Aided Design Time-Constrained Loop Pipelining Sanchez;Jordi cortadella.
  33. 2nd International Conference on Massively Parallel Computing Systems (MPCS'96) Maximum-Throughput Software Pipelining Sanchez;J. Cortadella
  34. Wai Lee
  35. Algorithm-Based Low-Power DSP System Design:Methodology and Verification VLSI Signal Processing Ⅷ A. Y. Wu;K. J. Liu;Z. Zhang;K. Nakajima;A. Raghuparthy;S. Liu
  36. Practical Low Power Digital VLSI Design G. Yeap