기능적 분해방법을 이용한 TLU형 FPGA의 다출력 함수 로직 합성 알고리즘 설계

Logic synthesis algorithm of multiple-output functions using the functional decomposition method for the TLU-type FPGA

This paper describes two algorithms for technology mapping of multiple output functions into interesting and pupular FPGAs(Field Programmable Gate Array) that use look-yp table memories. For improvement of technology mapping for FPGA, we use the functional decompoition method for multiple output functions. Two algorithms are proposed. The one is the Roth-Karpalgorithm extended for multiple output functions. The other is the efficient algorithm which looks for common decomposition functions through the decomposition procedure. The cost function is used to minimize the number of CLBs and nets and to improve performance of the network. Finally we compare our new algorithm with previous logic design technique. Experimental resutls show sigificant reduction in the number of CLBs and nets.