References
- The International Conference on Computer Design Boolean satisifiability and equivalence checking general binary decisioh disgrams P.Asher;S.Devadas;A.Ghosh
- IMEC-IFIP International Workshop on Applied Formal Methods for Correct VLSI Design v.2 Using TACHE for proving circuits C.ayol.;J.Pailet.
- ACM Computing Surveys v.24 no.3 Symbolic boolean manipulation with ordered binary-decision disgrams R.E.Bryant
- IEEE Trans. on computers v.C-35 no.8 Graph-based algorithms for boolean function mainpulation R.e.Bryant.
- Journal of Symbolic Computation v.4 Embedding Boolean expressions into logic programming W.Buttner.;H.Simonis.
- Proceedings in the International Conference on fifth Generation Computer Systems FGCS-88 The constraint logic programming language CHIP M.Dincbas;P.V.Hententyck;H.Himonis.A.Aggoun;T.Graf;F.Berthier
- IEEE Trans. on Computer-Aided Design of Integrated Circuits and systems v.12 no.1 Variable ordering algorithms for ordered binary decision diagrams and their evaluation M.Fujita;H.Fujisawa;Y.Masunaga
- Computers and Intractability: A Guide to the Theory of NP-completeness M.R.Garey.;D.S.Johnson.
- SIAM J. Comput v.18 CNf satisfiability test by counting and polynomial average time K.Iwama.
- IMEC-IFIP Inyernational Workshop on applied Formal Methods for Correct VLSI Design v.2 Tautology checking benchmarks: results with TC P.Lammens;L.Claesen;H.D.Man
- Bell System Tech. J. v.35 no.6 Minimization of Boolean functions E.J.Jr.McCluskey
- Internal Workshop on Discrete Algotithms and Complexity Random satisifiability problems P.Purdom
- Am. Math. Monthly v.59 no.8 The Problem of simplifying truth functions W.V.Quine.
- Computer Logic, Testing and Verification J.P.Roth
- Trans. AIEE v.57 A symbolic analysis of elay and swiching circuits C.E.Shannon
- IMEC-IFIP Inyernational Workshop on Applied Formal Methods for Correct VLSI Design v.2 Circuit verification in CHIP:Benchmark results H.Simonis.;T.L.Provost.
- Information Processing Letters v.37 A dual algorithm for the satisfiability problem Y.Tanaka
- Journal of Automated Reasoning v.10 no.1 Simplification in a satisfiability checker for VLSI applications F.Vlach
- J. ACM v.35 no.2 On the complexity of branching programs and decision trees for functions I.Wegener.