A Study on Optimal Synthesis of Multiple-Valued Logic Circuits using Universal Logic Modules U$_{f}$ based on Reed-Muller Expansions

Reed-Muller 전개식에 의한 범용 논리 모듈 U$_{f}$ 의 다치 논리 회로의 최적 합성에 관한 연구

In this paper, the optimal synthesis algorithm of multiple-valued logic circuits using universal logic modules (ULM) U$_{f}$ based on 3-variable ternary reed-muller expansions is presented. We check the degree of each varable for the coefficients of reed-muller expansions and determine the order of optimal control input variables that minimize the number of ULM U$_{f}$ modules. The order of optimal control input variables is utilized the realization of multiple-valued logic circuits to be constructed by ULM U$_{f}$ modules based on reed-muller expansions using the circuit cost matrix. This algorithm is performed only unit time in order to search for the optimal control input variables. Also, this algorithm is able to be programmed by computer and the run time on programming is O(p$^{n}$ ).