A new scheme for VLSI implementation of fast parallel multiplier using 2x2 submultipliers and ture 4:2 compressors with no carry propagation

부분곱의 재정렬과 4:2 변환기법을 이용한 VLSI 고속 병렬 곱셈기의 새로운 구현 방법

In this paper, we propose a new scheme for the generation of partial products for VLSI fast parallel multiplier. It adopts a new encoding method which halves the number of partial products using 2x2 submultipliers and rearrangement of primitive partial products. The true 4-input CSA can be achieved with appropriate rearrangement of primitive partial products out of 2x2 submultipliers using the newly proposed theorem on binary number system. A 16bit x 16bit multiplier has been desinged using the proposed method and simulated to prove that the method has comparable speed and area compared to booth's encoding method. Much smaller and faster multiplier could be obtained with far optimization. The proposed scheme can be easily extended to multipliers with inputs of higher resolutions.