고장시뮬레이션의 병렬화 알고리듬에 관한 연구

Study on parallel algorithmfor falult simulation

As design of very large circuits is made possible by rapid development of VLSI technologies, efficient fault simulation is needed. Ingeneral, fault simulation requires many computer resources. As general-purpose multiprocessors become more common and affordable, these seem to be an attractive and effective alternative for fault simulation. Efficient fault simulation of synchronous sequential circuits has been reported to be attainably by using a linear iterative array model for such a circuit, and combining parallel fault simulation with russogate fault simulation. Such fault simulation algorithm is parallelized on a general-purpose multiprocessor with shard memory for acceleration of fault simulation. Through the experimenal study, the effect of the number of processors on speed-up of simulation, processor utilization, and the effect of multiprocessor hardware on simulation performance are studied. Some results for experiments with benchmark circuits are shown.