디지털 지연동기루프의 설계 및 구현

Design and implementation of digital delay locked loop

  • 박형근 (고려대학교 전자공학과) ;
  • 김성철 (고려대학교 전자공학과) ;
  • 차균현 (고려대학교 전자공학과)
  • 발행 : 1996.08.01

초록

In this paper, Digital Delay Locked Loop(DDLL) is designed, implemented and analysed by experiment whose results show that it is possible to track the received signal by this scheme. Designed digital DLL has an advantage that it is not needed to maintain gain balance between early and late channels, which has been problem with an analog DLL. Also DDLL has more improved noise performance compared to analog DLL due to noise level limitation and noise cancellation characteristics. For various loop parameters, their effects on loop performance are analysed and simulated. Proposed DDLL is the first attempt as a digital approach in code tracking loop and it is expected to be a good reference for spread spectrum communication research.

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