전자공학회논문지B (Journal of the Korean Institute of Telematics and Electronics B)
- 제33B권9호
- /
- Pages.62-69
- /
- 1996
- /
- 1016-135X(pISSN)
비트 레벨 일차원 시스톨릭 모듈러 승산
Bit-level 1-dimensional systolic modular multiplication
초록
In this paper, the bit-level 1-dimensional systolic array for modular multiplication is designed. First of all, the parallel algorithm and data dependence graph from walter's method based on montgomery algorithm suitable for array design for modular multiplication is derived. By the systematic procedure for systolic array design, four 1-dimensional systolic arrays are obtained and then are evaluated by various criteria. As it is modified the array which is derived form [0,1] projection direction by adding a control logic and it is serialized the communication paths of data A, optimal 1-dimensional systolic array is designed. It has constant I/O channels for expansile module and it is easy for fault tolerance due to unidirectional paths. It is suitable for RSA cryptosystem which deals iwth the large size and many consecutive message blocks.
키워드