저항성 단락과 개방 결함을 갖는 메모리에 대한 동작분석과 효율적인 테스트 알고리즘에 관한 연구

A study on behavioral analysis and efficient test algorithm for memory with resistive short and open defects

To increase the functionality of the memories, previous studies have deifned faults models and proposed functional testing algorithms with low complexity. Although conventional testing depended strongly on functional (voltage) testing method, it couldn't detect short and open defects caused by gate oxide short and spot defect which can afect memory reliability. Therefore, IDDQ (quiescent power supply current) testing is required to detect defects and thus can obtain high reliability. In this paper, we consider resistive shorts on gate-source, gate-drain, and drain-source as well as opens in mOS FET and observe behavior of the memory by analyzing voltage at storge nodes of the memory and IDDQ resulting from PSPICE simulation. Finally, using this behavioral analysis, we propose a linear testing algorithm of complexity O(N) which can be applicable to both functional testing and IDDQ testing simultaneously to obtain high functionality and reliability.